Search - digital vhdl clock

[VHDL-FPGA-Verilog] Exp4-Clock

Description: 数字计时器，使用VHDL语言编写，使用数码管显示，精确到ms-digital timer, the use of VHDL development, the use of digital control, the precision of the ms
Platform: | Size: 808960 | Author: 萧飒 | Hits:

[Embeded-SCM Develop] VHDL

Description: VHDL数字钟数字电子钟此数字电子钟具有的功能包括： 1. 计时，时、分、秒显示； 2. 十二小时与二十四小时之间的转换； 3. 上下午显示； 4. 对时、分、秒的校时功能；-VHDL digital clock digital clock digital electronic clock with this function include: 1. Time, hours, minutes and seconds display 2. 12 hours and 24 hours between the conversion 3. On the afternoon show 4. hours, minutes and seconds of the school function
Platform: | Size: 3072 | Author: HJGJGHK | Hits:

[Software Engineering] clock

Description: 基于vhdl的数字钟有闹钟,秒表,时钟,日期等功能秒表可以开始,暂停,清零, 时钟可以设置时间, 还可以设置日期-VHDL based on the digital clock has an alarm clock, stopwatch, clock, date, stopwatch functions can start, pause, cleared, the clock can be set-up times, you can set the date
Platform: | Size: 3072 | Author: 张廷 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 这是一个实现时分秒的时钟功能的源码，采用vhdl语言编写，已写好led驱动，可直接在数码管上显示-Realize this is an accurate clock function when the source code, the use of VHDL language has been written led drive directly in the digital tube display
Platform: | Size: 246784 | Author: xiaoshuai | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟的VHDL源程序，可实现整点报时、闹钟的功能，还有常有星期的显示，已调试过-Digital Clock in VHDL source code, enabling the whole point timekeeping, alarm clock function, there are often weeks of shows that have been debug
Platform: | Size: 1339392 | Author: 玉峰 | Hits:

[VHDL-FPGA-Verilog] CLOCK

Description: 可以调整时间和设置闹钟的数字钟(VHDL)-Can adjust the time and set the digital clock alarm clock (VHDL)
Platform: | Size: 906240 | Author: iyoung | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟的程序，功能说明如下所示： 1.完成秒／分／时的依次显示并正确计数； 2.秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位； 3.定时闹钟：实现整点报时，通过语音设备来实现具体的报时； 4.时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整 5.可以选择使用12进制计时或者24进制计时。使用QuartusII6.0编译仿真通过，语言使用的是VHDL，可以方便的移植到其他的平台上面。 -Digital clock procedures, functional description is as follows: 1. Completed sec/min/h and the sequence shows the correct count 2. Sec/min/h in the paragraphs of the correct 10-bit full binary, seconds/minutes to achieve the age of 60 to the forward position 3. regular alarm clock: realize the whole point of time, through the voice equipment to realize specific time 4. time settings, which is manually adjusted when the function: When the clock does not consider accurate, they can respectively sub/clock adjust 5. can choose to use 12 or 24 hexadecimal hexadecimal time time. QuartusII6.0 simulation through the use of compiler, language used is VHDL, can be easily ported to other platforms above.
Platform: | Size: 232448 | Author: 余宾客 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字秒表的设计，reset为归零设置，start为重新计时设置-Design of digital stopwatch, reset to zero settings, start time set for the re-
Platform: | Size: 309248 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] clock

Description: 数字钟设计，有分秒显示，上下午显示，可下载到FPGA板子上进行数字显示哦-Digital clock design, there are minutes and seconds display, on the afternoon of shows can be downloaded to the FPGA on the board figures show Oh
Platform: | Size: 3072 | Author: 幸福 | Hits:

[assembly language] clock

Description: 描述了24小时计时的数字钟，同时具有分秒计时的功能-Described a 24-hour digital time clock, at the same time every minute timer function
Platform: | Size: 11264 | Author: 金珊珊 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 用高速硬件语言VHDL设计的全功能数字钟，经测试运行稳定-VHDL language used high-speed hardware design full-function digital clock, tested and stable operation
Platform: | Size: 2048 | Author: 李鑫 | Hits:

[Other] CLOCK

Description: 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital clock. The main function of the completion are: time function, 24-hour time display through the Seven-Segment LED dynamic display time school settings function, can be set hours, minutes, seconds the stopwatch to start, stop, and maintain display and removal.
Platform: | Size: 182272 | Author: 张保平 | Hits:

[Embeded-SCM Develop] vhdl-digital-clock-design

Description: 设计一个具有特定功能的数字电子钟。准确计时，以数字形式显示h、min、s 的时间。小时的计时要求为二十四进位，分和秒的计时要求为六十进位。该电子钟上电或按键复位后能自动显示系统提示00-00-00，进入时钟准备状态；第一次按电子钟功能键，电子钟从0时0分0秒开始运行，进入时钟运行状态；再次按电子钟功能键，则电子钟进入时钟调整状态，此时可利用各调整键调整时间，调整结束后可按功能键再次进入时钟运行状态。 -Designed with a specific function of a digital electronic clock. Accurate timing to the digital form h, min, s time. Hours of time requested for the 24 binary, minutes, and seconds of time requested for the 60 binary. The electronic bell power or reset button can automatically display 00-00-00 prompted, enter the clock readiness the first time by e-bell function keys, the electronic bell from 00:00:00 to start running, enter the clock running again by e-bell function keys, the electronic bell to enter the clock adjustment status, at this time can use the adjustment button to adjust the time to adjust after the end of function keys can be re-entering the clock running.
Platform: | Size: 6144 | Author: andy | Hits:

[VHDL-FPGA-Verilog] alarm-clock

Description: 基于vhdl的数字闹钟的设计。可实现计时、闹钟、调节时间功能。可以在FPGA上实现。-VHDL-based digital alarm clock design. Can achieve a time, alarm clock, adjust time function. FPGA implementation can be on.
Platform: | Size: 2048 | Author: tony | Hits:

[VHDL-FPGA-Verilog] clock

Description: 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 多功能数字钟-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock
Platform: | Size: 1024 | Author: 许毅民 | Hits:

[assembly language] clock

Description: 数字钟是采用数字电路实现“时”、“分”、“秒”数字显示的计时装置。由于数字集成电路的发展和石英晶体震荡器的使用，使得数字钟的精度、稳定度远远超过了机械钟表，已成为人们日常生活中必不可少的必需品。-Digital Clock is a digital circuit implementation, " when" , " sub" , " second" The figures show that the timing device. Digital integrated circuits because of the development and use of quartz crystal oscillator, making the accuracy of the number of minutes, far exceeding the stability of mechanical clocks and watches, has become essential daily necessities.
Platform: | Size: 338944 | Author: 庄青青 | Hits:

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[VHDL-FPGA-Verilog] Exp4-Clock

[Embeded-SCM Develop] VHDL

[Software Engineering] clock

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] CLOCK

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] clock

[assembly language] clock

[VHDL-FPGA-Verilog] clock

[Other] CLOCK

[Embeded-SCM Develop] vhdl-digital-clock-design

[VHDL-FPGA-Verilog] alarm-clock

[VHDL-FPGA-Verilog] clock

[assembly language] clock

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] vhdl-clock

[VHDL-FPGA-Verilog] clock

[VHDL-FPGA-Verilog] digital-electronic-clock

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