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[Other resource1_061115131201

Description: 数字边沿鉴相器 verilog源程序 -figures for 2500 phase-2500 verilog source digital phase detector verilog source
Platform: | Size: 9056 | Author: mingming | Hits:

[VHDL-FPGA-Verilog1_061115131201

Description: 数字边沿鉴相器 verilog源程序 -figures for 2500 phase-2500 verilog source digital phase detector verilog source
Platform: | Size: 9216 | Author: mingming | Hits:

[Software Engineering111

Description: 数字鉴相器,数字锁相环频率合成系统FPGA的实现,很有借鉴价值-Digital phase detector, digital PLL frequency synthesizer system FPGA realization of referential value
Platform: | Size: 53248 | Author: 颜小山 | Hits:

[OtherH9200

Description: H9200是一款商品防盗EAS主板,用于商场、服装,超市等场所的防盗产品,本产品采进了先进的数字检波技术,自动增益控制技术(AGC技术),锁相环(PLL)等技术,与以同类产EAS产品相比,有性价比高,误报率低,检测率高,反应速度快,结构更加合理,性能更加稳定等优点!-EAS H9200 motherboard manual, H9200 is a used for shopping malls, clothing, supermarkets and other places of the anti-theft products, the products taken into the advanced digital detector technology, AGC Technology (AGC technology), phase-locked loop (PLL) such as technology, with production of similar products, compared EAS, there are cost-effective, low false alarm rate, detection rate, response speed, the structure more reasonable and more stable performance and so on.
Platform: | Size: 577536 | Author: | Hits:

[VHDL-FPGA-Verilogcode

Description: it is the collection of the modules involved inthe design of digital fm.the code coves the key components like numerically controlled oscillator, loop filter, fir filter ,phase detector along with the complete cicuit implementation of the digital fm and the test bench of it.
Platform: | Size: 5120 | Author: syamprasad | Hits:

[VHDL-FPGA-Verilogdpll

Description: 基于Verilog的数字锁相环。包括三个模块,数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
Platform: | Size: 668672 | Author: 栾帅 | Hits:

[Program docDPLL

Description: 数字锁相环频率合成器的设计,鉴相器、环路滤波器、数控振荡器、反馈分频器-Digital PLL frequency synthesizer, phase detector, loop filter, NCO, feedback divider
Platform: | Size: 798720 | Author: taotao | Hits:

[Embeded-SCM DevelopDPLLdesign

Description: 数字锁相环频率合成器的设计,数字鉴相器,数字滤波器,数控振荡器,反馈分频器-Digital PLL frequency synthesizer, digital phase detector, digital filter, digital control oscillator, the feedback divider
Platform: | Size: 798720 | Author: taotao | Hits:

[OtherVerilog-Code

Description: Verilog source code by James Patchell: - Delta Sigma Modulator for doing Digital->Analog Conversion - Aquad-bquad phase detector - Uart Reciever - Uart Transmitter - One shot
Platform: | Size: 7168 | Author: happyuser | Hits:

[VHDL-FPGA-Verilogdpll1600e

Description: 数字锁相环的设计,包括鉴相器,环路滤波器,spi口输出,分频器的源代码-Digital phase-locked loop design source code, including the phase detector, loop filter, spi port output divider
Platform: | Size: 370688 | Author: zhujianhua | Hits:

[matlabPhase-Locked-Loop.rar

Description: charge pump phase-locked loop with digital phase-frequency detector,charge pump phase-locked loop with digital phase-frequency detector matalab model
Platform: | Size: 456704 | Author: my name | Hits:

[LabViewDigital-phase-sensitive-detector

Description: 基于labview8.6的数字相敏检波算法源码,高精度实现测量低信噪比条件下正弦波幅值和初相的测量-Sine wave amplitude and the initial phase of the measuring low signal-to-noise ratio under the conditions measurement labview8.6-based digital phase-sensitive detection algorithm source, high-precision
Platform: | Size: 19456 | Author: 罗知亮 | Hits:

[VHDL-FPGA-VerilogDCO_ST

Description: 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
Platform: | Size: 1024 | Author: 刘超 | Hits:

[VHDL-FPGA-VerilogDPLL_TEST

Description: 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
Platform: | Size: 1024 | Author: 刘超 | Hits:

[LabViewDigital-phase-sensitive-detector

Description: 基于labview8.6的数字相敏检波算法源码,高精度实现测量低信噪比条件下正弦波幅值和初相的测量-Based labview8.6 digital phase-sensitive detection algorithm source code, to achieve high-precision measurement of the amplitude and the initial phase of the sine wave measured under low SNR
Platform: | Size: 215040 | Author: 潘颖 | Hits:

[VHDL-FPGA-Verilogdpll

Description: 用verilog编写的全数字锁相环,包括鉴相器,模K计数器,加减脉冲模块和分频模块,都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
Platform: | Size: 6144 | Author: chi zhang | Hits:

[Otherdigital-phase-detector--FPGA

Description: Design of a new digital phase detector based on FPGA
Platform: | Size: 1526784 | Author: 595400 | Hits:

[Other Embeded programcostas

Description: 基于costas环路的载波同步,使收发时钟频率和相位一致,环路包括四个部分乘法器和低通滤波、鉴相器、环路滤波器和数字振荡器组成-Based on the carrier synchronization of Costas loop, the frequency and phase of the transmit and receive clock is the same. The loop consists of four parts, including the multiplier and low-pass filter, phase detector, loop filter and digital oscillator.
Platform: | Size: 1024 | Author: panda | Hits:

[LabViewDPD_Digital-phase-detector

Description: This the phase difference calculation method based on digital phase detector DPD. It uses Hilbert transform to shift one signal the other by 90 degree. Then by some manipulation, extract the phase difference between two signals.-This the phase difference calculation method based on digital phase detector DPD. It uses Hilbert transform to shift one signal the other by 90 degree. Then by some manipulation, extract the phase difference between two signals.
Platform: | Size: 54272 | Author: fethy16 | Hits:

[matlabpll

Description: 基于matlab的数字pll实现,鉴相器,滤波器以及压控震荡器组成,具备良好的锁相功能,适合入门学习(Digital PLL based on MATLAB, phase detector, filter and voltage controlled oscillator, phase lock function has good, suitable for beginners to learn)
Platform: | Size: 17408 | Author: qiya2 | Hits:
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