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[Software Engineeringcpu-16-vhdl

Description: 16位cpu的vhdl源代码。 自己看看,没有注释。-16 cpu vhdl the source code. See for yourself, not Notes.
Platform: | Size: 94995 | Author: 童宗挺 | Hits:

[Other resourceCPU

Description: 简单的16位CPU的VHDL设计 vhdl代码和cpu设计过程
Platform: | Size: 1489655 | Author: kilva | Hits:

[Other resource8-cpu

Description: 8位CPU的VHDL设计,16条指令系统,以及部分测试代码,开发工具是quartusii_60_pc
Platform: | Size: 2883 | Author: FJ | Hits:

[VHDL-FPGA-Verilogcpu16

Description: 一个16位cpu的vhdl代码。具体内容我也不清楚,自己慢慢研究吧-a 16 cpu of VHDL code. Specific content is not clear to me that their study it slowly
Platform: | Size: 3072 | Author: 王林 | Hits:

[VHDL-FPGA-VerilogcpuTerminate

Description: 用VHDL 编写的一个16位的cpu 设计方案,可以执行8条指令。-use VHDL to prepare a 16 cpu design of the program, the implementation of eight instructions.
Platform: | Size: 2108416 | Author: 宋文强 | Hits:

[VHDL-FPGA-Verilogthe-design-of-16-bit-cpu

Description: 用vhdl硬件语言设计的16位cpu,上传的压缩包既包含源代码又包含详细的文档说明。-with vhdl hardware design language of the 16 cpu, Upload compressed contains both the source code also contains a detailed document shows.
Platform: | Size: 128000 | Author: 晶晶 | Hits:

[Software Engineeringcpu-16-vhdl

Description: 16位cpu的vhdl源代码。 自己看看,没有注释。-16 cpu vhdl the source code. See for yourself, not Notes.
Platform: | Size: 95232 | Author: 童宗挺 | Hits:

[VHDL-FPGA-VerilogVHDL-XILINX-EXAMPLE26

Description: [VHDL经典设计26例]--在xilinx芯片上调试通过--[01--1位全加器][02--2选1多路选择器][03--8位硬件加法器][04--7段数码显示译码器][05--8位串入并出寄存器][6--8位并入串出寄存器][7--内部三态总线][8--含清零和同步时钟使能的4位加法计数器][9--数控分频器][10--4位十进制频率计][11--译码扫描显示电路][12--用状态机实现序列检测器的设计][13--用状态机对ADC0832电路控制实现SIN函数发生器][14--用状态机实现ADC0809的采样电路设计][15--DMA方式A/D采样控制电路设计][16--硬件电子琴][17--乐曲自动演奏][18--秒表][19--移位相加8位硬件乘法器][20--VGA图像显示控制器(彩条)][21--VGA图像显示控制器][22--等精度频率计][23--模拟波形发生器][24--模拟示波器][25--通用异步收发器(UART)][26--8位CPU设计(COP2000)]
Platform: | Size: 3687424 | Author: hawd | Hits:

[VHDL-FPGA-Verilogalu

Description: 16位RISC CPU的ALU,使用VHDL编写-16-bit RISC CPU
Platform: | Size: 2048 | Author: 李斌 | Hits:

[VHDL-FPGA-VerilogCPU

Description: 简单的16位CPU的VHDL设计 vhdl代码和cpu设计过程-Simple 16-bit CPU design of the VHDL code and VHDL design process cpu
Platform: | Size: 1488896 | Author: kilva | Hits:

[VHDL-FPGA-VerilogMyCPU16

Description: 16位cpu设计VHDL源码,其中包括alu,clock,memory等部分的设计-16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
Platform: | Size: 1089536 | Author: 孙冰 | Hits:

[VHDL-FPGA-Verilog8-cpu

Description: 8位CPU的VHDL设计,16条指令系统,以及部分测试代码,开发工具是quartusii_60_pc-8-bit CPU of the VHDL design, 16 instruction, as well as some of the test code, development tools is quartusii_60_pc
Platform: | Size: 3072 | Author: FJ | Hits:

[VHDL-FPGA-VerilogCPU16

Description: 用VHDL语言开发的一个16位的具有5级流水线的CPU设计-VHDL language used to develop a 16 with five lines of the CPU design
Platform: | Size: 417792 | Author: luanjinlong | Hits:

[OS program16cpu

Description: 实现16位的cpu设计 内容使用verilog hdl实现,具体的实现步骤方法,都已经写到文档里面去了!-To achieve 16-bit design of the contents of the cpu using verilog hdl achieve, the specific methods to achieve these steps have already been written inside the document went to!
Platform: | Size: 440320 | Author: gimel_sh | Hits:

[OS programCPU

Description: CPU编程,比较低层的硬件编程的 chm 资料文件--
Platform: | Size: 2714624 | Author: 张希行 | Hits:

[VHDL-FPGA-Verilogcpu-16-vhdl

Description: 用vhdl语用实现简单的16位cpu功能-Pragmatic use vhdl simple function of 16-bit cpu
Platform: | Size: 95232 | Author: 陈曦 | Hits:

[SCMESAM_CARD

Description: CPU卡程序 已经在电表应用 性能良好 适合国网要求的协议-CPU card procedures have been well-suited to the meter application performance requirements of an agreement State Grid
Platform: | Size: 6144 | Author: taxiangren80 | Hits:

[VHDL-FPGA-VerilogCPU

Description: 用VHDL编的简易16位和8位CPU,可完成加减乘法移位等功能,拥有源码和设计文档,资料齐全-Compiled with VHDL simple 16-bit and 8-bit CPU, to be completed by addition and subtraction multiplication shift functions, with source code and design documents, data and complete
Platform: | Size: 1489920 | Author: 雄鹰 | Hits:

[VHDL-FPGA-Verilogcpu

Description: 16位的CPU的VHDL程序~~还有附加的生成波形,可以应用于课程设计中-16-bit CPU, VHDL ~ ~ There are additional procedures for generating waveforms, can be applied to curriculum design
Platform: | Size: 1053696 | Author: liuying | Hits:

[VHDL-FPGA-VerilogCPU

Description: 16位简单cpu用VHDL语言实现。里面有好几个的》-16-bit cpu with a simple VHDL language. There are several of the "
Platform: | Size: 3181568 | Author: pjj | Hits:
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