Description: 工作原理：
脉冲输入，记录30个脉冲的间隔时间（总时间），LED显示出来，牵涉到数码管的轮流点亮，以及LED的码。输入端口一定要用个
74LS14整一下，图上没有。数码管使用共阴数码管。MAXPLUS编译。
测试时将光电门的信号端一块连接到J2口的第三管脚，同时第一管脚为地，应该与光电门的地连接（共地）。
开始测试：
按下按键，应该可以见到LED被点亮，指示可以开始转动转动惯量盘，等遮光片遮挡30次光电门后，
LED熄灭，数码管有数字显示，此为时间值，单位为秒，与智能计时器的连续脉冲测试模式中的T30值进行比较。
再按下按键即可进行下一次测量。
水平有限，见笑。-principle : pulse input, recording 30 pulse interval (total time), the LED display and digital control involves rotating lights, and LED yards. Input port must use the entire 000 74LS14 that there is no map. Digital control the use of digital control were overcast. Segments compiler. Test the door to the photoelectric signal an end connected to the mouth of the third J2 pins, for the first pin, should the photoelectric doors to connect (to a total). Testing : press the button, should be able to see the LEDs are lit, instructions to start the rotation inertia set, films such as shading block 30 photoelectric doors, the LED is off, digital possession figures show that for the time value of this unit for seconds Intelligent timer with a continuous pulse mode testing of T30 values were compare Platform: |
Size: 644978 |
Author:高颖峰 |
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Description: 工作原理：
脉冲输入，记录30个脉冲的间隔时间（总时间），LED显示出来，牵涉到数码管的轮流点亮，以及LED的码。输入端口一定要用个
74LS14整一下，图上没有。数码管使用共阴数码管。MAXPLUS编译。
测试时将光电门的信号端一块连接到J2口的第三管脚，同时第一管脚为地，应该与光电门的地连接（共地）。
开始测试：
按下按键，应该可以见到LED被点亮，指示可以开始转动转动惯量盘，等遮光片遮挡30次光电门后，
LED熄灭，数码管有数字显示，此为时间值，单位为秒，与智能计时器的连续脉冲测试模式中的T30值进行比较。
再按下按键即可进行下一次测量。
水平有限，见笑。-principle : pulse input, recording 30 pulse interval (total time), the LED display and digital control involves rotating lights, and LED yards. Input port must use the entire 000 74LS14 that there is no map. Digital control the use of digital control were overcast. Segments compiler. Test the door to the photoelectric signal an end connected to the mouth of the third J2 pins, for the first pin, should the photoelectric doors to connect (to a total). Testing : press the button, should be able to see the LEDs are lit, instructions to start the rotation inertia set, films such as shading block 30 photoelectric doors, the LED is off, digital possession figures show that for the time value of this unit for seconds Intelligent timer with a continuous pulse mode testing of T30 values were compare Platform: |
Size: 645120 |
Author:高颖峰 |
Hits:
Description: 上海外滩看到的最大的LED显示屏的内核源代码，主要是完成视频信号的远距离传输的编解码与接口转换-Shanghai Bund to see the largest LED display in the kernel source code, mainly to complete the long-distance video signal transmission codec conversion and interface Platform: |
Size: 484352 |
Author:liao |
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Description: 这是一个verilog HDL 语言的例子，在CPLD器件EPM240上实现了 RS232协议、按键处理、LED数码管显示和每秒加1数码显示。使用quartus ii 7.0 以上打开.-This is an example of verilog HDL language in the CPLD device EPM240 achieved RS232 agreement, deal button, LED digital tube display and digital display plus 1 per second. Quartus ii 7.0 use more than open. Platform: |
Size: 521216 |
Author:白蚁 |
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Description: 利用CPLD控制六个数码管动态显示所要显示的数值-CPLD to control the use of six LED dynamic display to display the numerical Platform: |
Size: 1024 |
Author:帅 |
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Description: 基于CPLD的VHDL语言数字钟（含秒表）设计
利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短（设计过程中即可实现时序仿真）、调试方便、故障率低、修改升级容易等特点。
本设计采用自顶向下、混合输入方式（原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计）实现数字钟的设计、下载和调试。
-CPLD based on the VHDL language digital clock (with stopwatch) design using a chip can be completed in addition to the clock source, buttons, speakers and display (LED) in addition to all functions of digital circuits. All digital logic functions are used in the CPLD device VHDL language. This design has a small and short design cycle (design process to achieve timing simulation), to facilitate debugging, fault rate is low and easy to modify the characteristics of the upgrade. The design uses a top-down, mixed input (input schematic- top-level file access and VHDL language input- the module program design) Design of digital clock, download and debug. Platform: |
Size: 95232 |
Author:wuhuisong |
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Description: 实现大型LED屏显示的CPLD程序，对FPGA学习很有帮助-To achieve large-scale LED screen display of the CPLD program, very helpful for learning FPGA Platform: |
Size: 1364992 |
Author:赵维 |
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Description: 利用kcpsm3控制lcd显示
平台：ise 10.1， picoblaze， Spartan3e 开发板
说明：综合按键和lcd、led的功能，思想简单，需要新技术，适合想在fpga方面深造的人。-using kcpsm3 for lcd display
platform: ise 10.1， picoblaze， Spartan-3E FPGA Starter Kit Board
comment: involve lcd/led/switch, simple mind but need up-to-date technics, suitable for who want to go deep in fpga development. Platform: |
Size: 1106944 |
Author:kn |
Hits:
Description: Verilog 编写的频率计，使用8位LED作为显示，Quartus II 6.0的工程文件。保证好用，EPM240T的芯片。使用了66 的资源。-Written in Verilog frequency counter, using 8-bit LED as the display, Quartus II 6.0 of the project file. To ensure easy to use, EPM240T chips. 66 of the resources used. Platform: |
Size: 585728 |
Author:石头 |
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Description: cpld项目电子时钟实训的原代码，分各个模块，实现计时，报时，led显示等-E-clock training cpld the original project code, sub-modules, to achieve timing, timer, led display Platform: |
Size: 119808 |
Author:往事随风 |
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Description: 吉大短学期CPLD实习程序
设计一个 4 路抢答器，当按下抢答键开始抢答，设置 4 个按键作为 4 路抢答开关，4 个LED 作为抢答显示，一旦抢答成功，蜂鸣器发声，与抢答开关对应的 LED 亮
-Chittagong short term internship program CPLD design a 4-way Responder, Responder to start when you press the answer in, set the four keys as the answer in 4-way switch, 4 LED display as a Responder, if answer in successfully, the buzzer sound, and answer in the corresponding LED light switch Platform: |
Size: 188416 |
Author:吴琦轩 |
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Description: 基于CPLD的DS18B20温度显示程序，可将采集到的温度值通过16位LED或四位数码管实时显示，同时可任意设定温度上下限，实现蜂鸣器告警（该程序已实测成功，内附DS18B20中文资料）-CPLD-based DS18B20 temperature display program can be collected by temperature or four 16-bit digital tube LED display real-time, while lower temperature can be set to achieve the alarm buzzer (the program has been successfully measured, included DS18B20 Chinese data) Platform: |
Size: 1101824 |
Author:CTK |
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Description: CPLD EMP240 程序。包括加法器，LED显示，串口，蜂鸣器，数码管动态显示等功能。-CPLD EMP240 program. Includes adders, LED display, serial port, a buzzer, dynamic digital tube display and other functions. Platform: |
Size: 4397056 |
Author:liu |
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Description: FPGA／CPLD技术是近年来计算机与电子技术领域的又一场革命。本书以Xilinx与Altera公司的FPGA／CPLD为主，详细介绍了FPGA／CPLD从芯片到MAX+plusⅡ、Quartus与ISE开发环境和Verilog／VHDL语言，并以交通灯逻辑控制、电子钟与点阵LED显示、LCD液晶显示及计算机ISA接口和PCI接口的设计等为例，由浅入深地详述了如何应用FPGA／CPLD进行电子设计。书中的大多数电路图和源程序已经过实例验证，读者可以直接应用于自己的设计。本书的特点是强调实用性和先进性，力求通俗易懂。
本书适用于计算机、电子、控制及信息等相关专业的在校大学生，对广大工程技术人员也具有实用价值。-FPGA/CPLD technology in recent years the field of computer technology and electronic another revolution. Book Xilinx and Altera' s FPGA/CPLD based, detailing the FPGA/CPLD from the chip to MAX+plus Ⅱ, Quartus and ISE development environment and Verilog/VHDL language and logic control traffic lights, electronic bell with dot matrix LED display , LCD liquid crystal display and computer ISA interface and PCI interface design, for example, progressive approach to detail how the application of FPGA/CPLD for electronic designs. Circuit and the source of most of the book have been instances of verification, the reader can be directly applied to their own design. Characteristic of this book is to emphasize the practical and advanced, best straightaway. This book applies to computers, electronics, control and information and other related professional college students, the majority of engineering and technical personnel also has practical value. Platform: |
Size: 5460992 |
Author:朱杞柠 |
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Description: 5个源码包括4输入16输出译码器、并入串出、带复位的六十进制、动态LED显示两个两个不同值、静态LED十六进制显示。-5 source coders include a 4-input and 16-output decoder, parallel-in and the string-out, sixty hex with reset, two LEDs display two different values dynamiclly, two LEDs display sixteen hex staticlly. Platform: |
Size: 3072 |
Author:齐程 |
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