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[Other resource] jcq

Description: max+plusII下的各种功能的计数器vhd-under the various functions of the counter vhd
Platform: | Size: 1135 | Author: 李清 | Hits:

[Other resource] count16

Description: count16.vhd 16位BCD计数器VHDL源程序-count16.vhd 16 BCD counter VHDL source
Platform: | Size: 841 | Author: 杨奎元 | Hits:

[Communication-Mobile] iic_vhdl

Description: iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist
Platform: | Size: 889991 | Author: benny | Hits:

[VHDL-FPGA-Verilog] key_counter

Description: 4X4 KEYPAD 的输入位数计数器，可以自己定义输入的位数-4x4 KEYPAD median counter input, input their own definition of the median
Platform: | Size: 159744 | Author: 分第三 | Hits:

[VHDL-FPGA-Verilog] jcq

Description: max+plusII下的各种功能的计数器vhd-under the various functions of the counter vhd
Platform: | Size: 1024 | Author: 李清 | Hits:

[VHDL-FPGA-Verilog] count16

Description: count16.vhd 16位BCD计数器VHDL源程序-count16.vhd 16 BCD counter VHDL source
Platform: | Size: 1024 | Author: 杨奎元 | Hits:

[Communication-Mobile] iic_vhdl

Description: iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist -IIC bus controller VHDL realize- VHDL Source Files: i2c.vhd- top level file i2c_control.vhd- control function for the I2C master/slave shift.vhd- shift register uc_interface.vhd- uC interface function for an 8-bit 68000-like uC upcnt4.vhd- 4-bit up counter i2c_timesim.vhd- post-route I2C simulation netlist
Platform: | Size: 889856 | Author: benny | Hits:

[Windows Develop] 11

Description: cnt6.bdf 六进制约翰逊计数器 counters.vhd 不同功能的简单计数器 count60.vhd 60进制计数器 count60.bdf 60进制计数器 counter_1024.vhd 8位二进制计数器 counter_1m.vhd 16位二进制计数器 counter.vhd N进制计数器-M Johnson cnt6.bdf six different functions counters.vhd counter simple counter count60.vhd 60 hexadecimal counter count60.bdf 60 hexadecimal counter counter_1024.vhd 8 bit binary counter counter_1m.vhd 16 bit binary counter counter.vhd N M-ary Counter
Platform: | Size: 7168 | Author: libing | Hits:

[VHDL-FPGA-Verilog] pinluji

Description: 四位十进制频率计设计 包含测频控制器（TESTCTL），4位锁存器(REG4B)，十进制计数器（CNT10）的原程序(vhd)，波形文件(wmf ),包装后的元件(bsf)。顶层原理图文件（Block1.bdf）和波形。 -Four decimal frequency meter measuring frequency controller design includes (TESTCTL), 4 bit latch (REG4B), decimal counter (CNT10) of the original procedure (vhd), waveform file (wmf), packaged components (bsf). Top-level schematic document (Block1.bdf) and waveform.
Platform: | Size: 11264 | Author: 深空 | Hits:

[OS program] vh2sc

Description: 将VHDL转换为C的软件 将VHDL转换为C的软件-VH2SC is a free basic VHDL to SystemC converter. The converter handles a small subset of Synthesisable VHDL 87/93 language constructs. The current version translates all VHDL IEEE types to sc_int/sc_uint/integers and booleans this in order to maximise performance. The aim of the converter is to produce a cycle accurate model of synthesisable VHDL code. The converter runs on Windows Example1: Simple counter Convert the counter.vhd file to SystemC, c:VHDL2SystemCexample1>vh2sc-v-mti count.vhd VH2SC-> VHDL to SystemC Converter Ver 0.21** Alpha Release** (c)HT-Lab 2007 SQLite Version : 3.3.13 Parsing File : count.vhd Line 9** Info : library ieee ignored Line 28** Info : VH2SC Translation Disabled Line 32** Info : VH2SC Translation Re-Enabled Line 37** Info : process() translated to process_line37 Writing Header File : cnt.h Writing C++ File : cnt.cpp ** Info : Modelsim SC_MODULE_EXPORT(cnt) macro added The-v is a verbose flag and-mti is requi
Platform: | Size: 819200 | Author: whiz | Hits:

[Windows Develop] 55_falsepath

Description: 地址计数器 请注意: 本例的各个源描述的编译顺序应该是: 55_falsepath.vhd 55_falsepath_stim.vhd-Address counter Please note: This case is described in various sources to compile the order should be: 55_falsepath.vhd 55_falsepath_stim.vhd
Platform: | Size: 2048 | Author: 朱琦 | Hits:

[VHDL-FPGA-Verilog] 74LS160

Description: 源码，VHDL语言编写的74LS160计数器-Source code, VHDL language of the 74LS160 counter
Platform: | Size: 50176 | Author: 周 | Hits:

[source in ebook] counter.vhd__

Description: counter.vhd- counter.vhd
Platform: | Size: 2048 | Author: cute | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc-clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc
Platform: | Size: 8192 | Author: sreejith | Hits:

[VHDL-FPGA-Verilog] 8-Bit-Up-Counter-With-Load

Description: 8位计数器与负荷 -----------------------8位计数器与负荷 -8-Bit Up Counter With Load 1------------------------------------------------------- 2-- Design Name : up_counter_load 3-- File Name : up_counter_load.vhd 4-- Function : Up counter with load 5-- Coder : Deepak Kumar Tala (Verilog) 6-- Translator : Alexander H Pham (VHDL) 7-------------------------------------------------------
Platform: | Size: 5120 | Author: 王浩 | Hits:

[VHDL-FPGA-Verilog] cnt10.vhd

Description: 设计一个10进制同步计数器，带一个清零端，一个进位输出端。（如果改成六进制，应该如何修改程序） 计数器分为同步计数器和异步计数器两种，是典型的时序电路，分析计数器就能更好的了解时序电路的特性。所谓同步计数器，就是在时钟脉冲的控制下，构成计数器的各触发器同时发生变化的那一类计数器。异步计数器又称行波计数器，它的下一位计数器的输出作为上一位计数器的时钟信号，这样一级一级串接起来就构成了一个异步计数器。异步计数器与同步计数器不同之处就在于时钟脉冲的提供方式，但是，由于异步计数器采用行波计数，从而使计数延迟增加，在要求延迟小的领域受到了很大的限制。尽管如此，由于它的电路简单，仍有广泛的应用。 输入：逻辑开关，单脉冲按钮。输出：LED灯。-Design of a 10-N synchronous counter, with a clear end, a carry output. (If you change the hex, it should be as Any amendment to the procedure) Divided into synchronous and asynchronous counter counter counter two, is a typical sequential circuit, analysis of the counter can better understand Timing characteristics of the circuit. The so-called synchronous counter, that is, under the control of the clock pulse, the counter triggers the same time constitute a change The kind of counter. Asynchronous counter, also known as traveling wave counter, it s next on the counter output as a counter clock signal No, this one a tandem together to form an asynchronous counter. Asynchronous counter and synchronous counter difference is that the clock Pulse mode of delivery, but because of the asynchronous counter using wave count, so count delayed increase in the required areas of the small delay Has been greatly restricted. However, because of its simple circuit, there are still widel
Platform: | Size: 1024 | Author: chenguoxian | Hits:

[VHDL-FPGA-Verilog] 74ls160

Description: 这是一个使用vhdl语言编写的74LS160计数器，具有同步置位，异步清零的功能。-This is a use vhdl language 74LS160 counter with synchronous set, asynchronous clear function.
Platform: | Size: 38912 | Author: | Hits:

[VHDL-FPGA-Verilog] Contador.vhd

Description: Counter of n-bits chosen by design
Platform: | Size: 1024 | Author: nanu000 | Hits:

[Other] DAC_Load

Description: Load DAC by SPI protocol -- Unit provides serial load of DAC trough SPI 3-wire serial interface -- It sends 24-bit word, format of the word: -- 4-bit command: C3-C0, 4x don t care bits, 12-bit data: d11-d0, 4x don t care bits -- -- Serial interface outputs: -- SDI - Serial Interface Data sent to DAC -- SCK - Serial Interface Clock -- CSLD - Serial Interface Chip Select/Load -- -- DAC word length = 24 bit: -- -------------------------- -- MSB -- 4 bits - DAC command -- 4 bits - don t care values -- 12 bits - "gain" word -- 4 bits - don t care values -- LSB -- -------------------------- -- -- Dependencies: -- -- This unit needs the following files: -- 1) counter.vhd -- 2) SEQUENCE.vhd -- 3) rising.vhd -- 4) falling.vhd -- 5) Dline1.vhd -- 4) useful.vhd -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments:-Load DAC by SPI protocol -- Unit provides serial load of DAC trough SPI 3-wire serial interface -- It sends 24-bit word, format of the word: -- 4-bit command: C3-C0, 4x don t care bits, 12-bit data: d11-d0, 4x don t care bits -- -- Serial interface outputs: -- SDI - Serial Interface Data sent to DAC -- SCK - Serial Interface Clock -- CSLD - Serial Interface Chip Select/Load -- -- DAC word length = 24 bit: -- -------------------------- -- MSB -- 4 bits - DAC command -- 4 bits - don t care values -- 12 bits - "gain" word -- 4 bits - don t care values -- LSB -- -------------------------- -- -- Dependencies: -- -- This unit needs the following files: -- 1) counter.vhd -- 2) SEQUENCE.vhd -- 3) rising.vhd -- 4) falling.vhd -- 5) Dline1.vhd -- 4) useful.vhd -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments:
Platform: | Size: 7168 | Author: Vladimir | Hits:

[VHDL-FPGA-Verilog] VHD-L-QUARTUS--Counter

Description: 基于QUARTUS软件的VHDL语言开发，文件中含有VHDL语言设计的分频器，加法减法计数器，并生成有原理图，只要有QUARTUS软件即可仿真运行。-VHDL QUARTUS Counter
Platform: | Size: 11118592 | Author: STAR LEE | Hits:
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