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[Internet-Networkcounter

Description: 用C++编写的计数器CGI程序,功能强大,运行速度快速可靠,计数器也可以隐藏,该CGI程序运行于WinNT/Intel平台-prepared by the Counter CGI program, a powerful, fast and reliable operating speed, counter can hide, The CGI program runs on WinNT / Intel platform
Platform: | Size: 107925 | Author: 林楠 | Hits:

[Othercounter

Description: 一个asp.net计数器-a asp.net arithmometer!
Platform: | Size: 2172 | Author: 刘军 | Hits:

[CSharpossybook

Description: 本次设计要求我使用最不经常使用页面淘汰算法。该算法在需要太太某一页是,首先淘汰到当前时间为止,被访问次数最少的那一页。这只要在页表中给每一页增设一个访问计数器即可实现。每当该页被访问时,访问计数器加1,而发生一次缺页中断时,则淘汰计数值最小的那一页,并将所有的计数器清零。-the design I use most frequently used pages out algorithm. The algorithm needs his wife to a certain page is the first out of the current period, the number of visits at least one of those. This page provided in the table for each additional page counter a visit can be realized. When the page was the visit, plus a visit counter, and once interrupted missing pages, then count out that one of the smallest, with all the counter reset.
Platform: | Size: 81042 | Author: 成子 | Hits:

[Othercounterxunjie

Description: 迅捷简易网页计数器 Ver2.0 一.系统要求: ASP+ACCESS 二.程序主要功能: 简单的页面计数功能。 三.使用方法 1. 上传全部文件; 2. 用记事本打开setup.asp更改程序按装路径; 3. 将 下面的代码添加到需要计数的网页, <script language=\"javascript\" src=\"count.asp\"></script> 其中count.asp应改为计数文件的实际路径。 四.文件说明 count.asp 计数器主文件. count.mdb ACCESS数据库. index.asp 计数器测试文件. -swift summary Ver 2.0 counter a website. System Requirements : ASP ACCESS two. Procedures main functions : a simple count of pages function. 3. The use of a method. Upload all the documents; 2. Use Notepad to open setup.asp changes in procedures installed by the path; 3. The following code will be added to the need to count the website lt; Script language = "javascript" src = "count.asp" gt; lt; / scriptgt; count.asp which documents should be changed to count the actual path. 4. This document explains count.asp counter master file. Count.mdb ACCESS database. Index.asp counter test documents.
Platform: | Size: 18276 | Author: 秦凯伦 | Hits:

[Process-Thread进程和线程

Description: 看一下UNIX系统中的进程和Mach的任务和线程之间的关系。在UNIX系统中,一个进程包括一个可执行的程序和一系列的资源,例如文件描述符表和地址空间。在Mach中,一个任务仅包括一系列的资源;线程处理所有的可执行代码。一个Mach的任务可以有任意数目的线程和它相关,同时每个线程必须和某个任务相关。和某一个给定的任务相关的所有线程都共享任务的资源。这样,一个线程就是一个程序计数器、一个堆栈和一系列的寄存器。所有需要使用的数据结构都属于任务。一个UNIX系统中的进程在Mach中对应于一个任务和一个单独的线程。 -look at the UNIX System and the process of Mach's mandate and the relationship between the threads. In UNIX systems, a process includes an executable program and a range of resources, such as file descriptors table and address space. In Mach, a task only a series of resources; Threads handle all the executable code. A Mach task can have any number of threads and its associated, and each one must thread related tasks. And to a certain set of tasks related to the threads are sharing all the resources. Thus, a thread is a program counter, a stack, and a series of registers. All need to use the data structures are covered by the mandate. A UNIX system in the process of Mach which corresponds to a mandate and a separate thread.
Platform: | Size: 20111 | Author: 朱善发 | Hits:

[Internet-Networkcounter

Description: 用C++编写的计数器CGI程序,功能强大,运行速度快速可靠,计数器也可以隐藏,该CGI程序运行于WinNT/Intel平台-prepared by the Counter CGI program, a powerful, fast and reliable operating speed, counter can hide, The CGI program runs on WinNT/Intel platform
Platform: | Size: 107520 | Author: 林楠 | Hits:

[Othercounter

Description: 一个asp.net计数器-a asp.net arithmometer!
Platform: | Size: 2048 | Author: 刘军 | Hits:

[WEB Code(counter)

Description: NET网站访问统计系统(counter),平台asp.net+c#,显示网站访问统计的简单例子。-NET website statistics system (counter), the platform Asp. Net c#, Statistics show that the site was visited by a simple example.
Platform: | Size: 1017856 | Author: 陈是 | Hits:

[CSharpcounter

Description: C#做的一个计算器小程序,供参考学习之用。-C# Done a calculator applet for reference learning.
Platform: | Size: 75776 | Author: mlw | Hits:

[CSharpcounter

Description: 相信很多人都可以做得一个计数器的程序,不论是用C#、VB、VC++等编程工具。在这里我所做的这个计数器是使用C#做的,效果可能可其他人所做的不一样。它主要的目的是通过等额还贷对买房子的客户分期付款的金额和要多少年限才能还清钱进行计算。-I believe many people could do a counter procedures, whether they are using C#, VB, VC++ And other programming tools. I have done here is to use the counter C# Do may be done by other people not the same. Its main objective is through the matching of buy a house loan repayment installments of the amount of customers and how many number of years in order to repay the money to make the calculation.
Platform: | Size: 63488 | Author: longlong | Hits:

[Windows Developcounter

Description: 详细描述n比特计数器及RTL验证,计数器的位宽用generic语句设置为参数。MY_CNTR是一个n比特二进制的计数器,可以向上向下计数,并可设置计数值,计数器用异步的方式进行低电平复-A detailed description of n-bit counter and RTL verification, the bit counter is set to use generic parameters statement. MY_CNTR is an n-bit binary counter, counting down to up, and set of values, counters with asynchronous low-level approach to rehabilitation
Platform: | Size: 10240 | Author: chixiaobin | Hits:

[Browser Clientcounter

Description: ASP编写的网页计数器,用于计算访客数量-ASP pages to prepare counter, used to calculate the number of visitors
Platform: | Size: 1024 | Author: lei | Hits:

[VHDL-FPGA-VerilogRipple_Carry_counter

Description: Ripple Carry Counter. the synchronous version of Ripple Counter. a bit less fasr version the ripple counter but a synchronmous one that will work well on FPGA. wrriten in behavioral VHDL.
Platform: | Size: 20480 | Author: avi | Hits:

[AlgorithmCounter

Description: Squeak Counter .. a nice example for little smalltak
Platform: | Size: 1024 | Author: rapboyx | Hits:

[Otherfpganaoz

Description: 基于FPGA闹钟系统的设计。 1.秒模块实际上是一个计数器,一秒记录一次并输出。 2.分,时模块在一个脉冲上升沿计数一次的基础上,加入了时间调整控制。 3.调整时间的控制模块,在使能信号有效时,才可实现时分的调整。 4.闹钟调整及控制模块,可实现闹钟设时的调节功能。 5.显示模块,实现时间与闹钟显示的切换。 6.闹铃模块,实现闹铃的发声装置。 7.总逻辑模块,实现电子闹钟相应功能的总系统。 -FPGA-based alarm system design. 1. Second module is actually a counter, a second recording and output. 2. Am, when the module is a pulse based on the rising edge of a count by adding the time to adjust control. 3. Adjust the time of the control module, the enable signal is active in order to achieve the hours of adjustments. 4. Alarm clock adjustment and control modules can be realized when the alarm clock set up regulatory function. 5. Display module to realize the time and alarm clock display switch. 6. Alarm module to achieve the alarm audible signal devices. 7. The total logic block to realize the corresponding function of the total electronic alarm system.
Platform: | Size: 197632 | Author: maominchao | Hits:

[SCMTimerCount1

Description: AVR重要定时计数器1的15种工作模式,包括普通,CTC,快速PWM,相位和频率可调PWM的典型应用-AVR important to counter a 15-time working modes, including normal, CTC, fast PWM, phase and frequency adjustable PWM Typical applications
Platform: | Size: 155648 | Author: zhenqi | Hits:

[matlabcounter

Description: Counter in Matlab we can create a counter on matlab with this program
Platform: | Size: 1024 | Author: chris | Hits:

[VHDL-FPGA-Verilogcounter

Description: 不同频率的两个计数器,第一个计数器向上技术,第二个当第一个计满后向下计数-Two different frequency counter, a counter up the first technical, the second when the first after the expiration of a count down
Platform: | Size: 5120 | Author: che | Hits:

[VHDL-FPGA-Verilogcounter

Description: -- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"--- Mod-16 Counter using JK Flip-flops -- Structural description of a 4-bit binary counter. -- The first two design entities describe a JK flip-flop and a 2-input AND gate respectively. -- These are then packaged together along with a signal named tied_high into a package named jkpack . -- The counter design uses the package jkpack , giving it access to the components and the signal declared within the package. -- The flip-flops and AND-gates are wired together to form a counter. -- Notice the use of the keyword OPEN to indicate an open-cct output port. -- some syntax can t be synthesized,it s for simulation only,such as "AFTER 5 ns"
Platform: | Size: 1024 | Author: jgc | Hits:

[VHDL-FPGA-VerilogAdder and Counter VHDL

Description: Source code of a full adder and a counter VHDL.
Platform: | Size: 178 | Author: hameye | Hits:
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