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[SCM] MAICHONGSHUCHU

Description: PIC单片机编写显示表头,用于测量脉冲输出式速度信号-PIC first table shows the preparation for measuring pulse output signal speed
Platform: | Size: 148480 | Author: 陈超 | Hits:

[VHDL-FPGA-Verilog] 9.3_Pulse_Counter

Description: 基于Verilog-HDL的硬件电路的实现 9.3 脉冲计数与显示 　　9.3.1 脉冲计数器的工作原理 　　9.3.2 计数模块的设计与实现 　　9.3.3 parameter的使用方法 　　9.3.4 repeat循环语句的使用方法 　　9.3.5 系统函数$random的使用方法 　　9.3.6 脉冲计数器的Verilog-HDL描述 　　9.3.7 特定脉冲序列的发生 　　9.3.8 脉冲计数器的硬件实现 -based on Verilog-HDL hardware Circuit of 9.3 pulse count and showed 9.3 .1 pulse counter the principle 9.3.2 Counting Module Design and Implementation para 9.3.3 meter usage 9.3.4 repeat cycle statement on the use 9.3.5- EC $ random function of the use of pulse counter 9.3.6 Verilog-HDL depiction 9.3.7 to specific pulse sequences occurred pulse counter 9.3.8 Hardware Implementation
Platform: | Size: 4096 | Author: 宁宁 | Hits:

[Software Engineering] design

Description: 本文介绍了采用VB语言编程，利用CAN现场总线技术以及华控RSM智能模块搭建分布式监控系统的逻辑结构，采用CAN2.0通讯协议实现上位机与模块的数据通信。详细介绍了RSM04隔离型脉冲输入计数器模块与上位计算机的连接与通讯实现。在实验过程中模拟了信号发生源，其发出的信号经模块采集后送至上位机，执行计数值程序后，可以读取计数结果。-This paper introduces the use of VB programming language, the use of CAN field bus technology and intelligent module RSM Hua control structures distributed control system logic structure, the use of communication protocols CAN2.0 realize Between PC and data communications module. Details RSM04 Counter Pulse Input Isolated Module and Host Computer realize the connection and communication. In the experiment to simulate the signal source, the signals collected by the module to the host computer, the implementation of numerical procedures, which can be read by the result of the calculation.
Platform: | Size: 65536 | Author: 李婷 | Hits:

[SCM] pulse

Description: 本程序实现了一个信号发生器。此信号发生器是由两个完全相同的可自加载加法计数器LCNT8组成，它的输出信号的高低电平脉宽可分别由两组8位预置数进行控制。-This procedure implements a signal generator. This signal generator is made up of two identical adder can be loaded from the counter LCNT8 composition, and its output signal high-low pulse width can be preset by the two groups of eight control number.
Platform: | Size: 1024 | Author: liushenshen | Hits:

[VHDL-FPGA-Verilog] d02

Description: 此程序为脉宽测量电路vhdl代码，能够对输入的脉冲信号用10HZ时钟进行计数，输出计数结果。主模块调用显示、计数、控制三个模块实现主体功能-This procedure for pulse width measurement circuit VHDL code, able to input the pulse signal with 10Hz clock count, the output result of the calculation. Main module calls show that counts, control the main functions of the three modules realize
Platform: | Size: 2048 | Author: jingken | Hits:

[SCM] Cymometer

Description: 低频频率计 实例目的：学习定时器、计数器、中断应用 说明：选用24MHz的晶体，主频可达2MHz。用T1产生100us的时标，T0作信号脉冲计数器。假设晶体频率没有误差，而且稳定不变（实际上可达万分之一）；被测信号是周期性矩形波（正负脉冲宽度都不能小于0.5us），频率小于1MHz，大于1Hz。要求测量时标1S，测量精度为0.1％。-Examples of low-frequency frequency meter Objective: To study timer, counter, interrupt Application Note: optional 24MHz crystal, frequency up to 2MHz. 100us generated by the T1 time scale, T0 for the signal pulse counter. Assuming there is no crystal frequency error, and stable (in fact up to one ten thousandth) the measured signal is periodic rectangular wave (positive and negative pulse width can not be less than 0.5us), the frequency of less than 1MHz, greater than 1Hz. Requested measurement time scale 1S, measurement accuracy of 0.1.
Platform: | Size: 2048 | Author: 王伟 | Hits:

[SCM] timer-counter

Description: 使用单片机的定时器定时功能，开发出来的脉冲发生器-The use of single-chip timer timer function, developed pulse generator
Platform: | Size: 1024 | Author: haizhu | Hits:

[assembly language] counter1

Description: 基於8951的計數器，用4位LED顯示，通過脈衝計數，每一個下降沿計數一個-8951 based on the counter, with four LED display, through the pulse count, each count a falling edge
Platform: | Size: 2048 | Author: 吳軍 | Hits:

[Other] labviewmaichongjishu

Description: 用labview实现的脉冲计数器达到技术的效果-Using LabVIEW achieved pulse counter the effects of technology
Platform: | Size: 8192 | Author: 玉林 | Hits:

[VHDL-FPGA-Verilog] COUNTER

Description: 对外部输入的高频脉冲信号进行分频，应用于FPGA/CPLD .-External input of high-frequency pulse signal frequency, applies to FPGA/CPLD.
Platform: | Size: 1024 | Author: fsdfe | Hits:

[VHDL-FPGA-Verilog] freqm

Description: 以CPLD器件EPM7128SLC84-15为核心实现的简易数字频率计，采用在一定时间内对数字脉冲计数的方法，可直接测量TTL电平的数字脉冲信号的频率、周期和脉宽。其他一些信号可经过信号预处理电路变换后测量。 量程：1Hz～999999Hz 输入信号：（1）TTL电平数字脉冲信号；（2）方波/正弦波，幅度0.5~5V 显示：七段数码管显示频率（Hz）和周期/脉宽（us） 控制：两个拨码开关切换三种工作模式：测频率，测周期，测脉宽-Frequency Counter realized with Altera EPM7128SLC84-15. It can measure frequecy, cycle and pulse width of TTL sigals.
Platform: | Size: 1053696 | Author: tom | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: PWM控制就是产生一定周期，占空比不同的方波信号，当占空比较大时，电机转速较高，否则电机转速较低。当采用FPGA产生PWM波形时，只需FPGA内部资源就可以实现，数字比较器的一端接设定值输出，另一端接线性递增计数器输出。当线性计数器的计数值小于设定值时输出低电平，当计数器大于设定值时输出高电平，这样就可通过改变设定值，产生占空比不同的方波信号，从而达到控制直流电机转速的目的。 直流电机控制电路主要由2部分组成，如图1所示：  FPGA中PWM脉宽调制信号产生电路；  FPGA中正/反转方向控制电路 -PWM control is a certain cycle, a different duty cycle square wave signal, when the duty cycle is high, higher motor speed, or lower motor speed. When the PWM waveform generated using FPGA, the FPGA internal resources only can be achieved, the figure one comparator output termination setting, the other linear incremental counter output termination. When the value of linear counter output is less than low-level settings, when the counter output is greater than high settings, so that by changing the settings can produce different duty cycle square wave signal, DC motor control to achieve the purpose of speed. DC motor control circuit mainly by 2 parts, as shown in Figure 1:  FPGA in the PWM pulse width modulation signal generator circuit Chiang Kai-shek  FPGA/reverse direction control circuit
Platform: | Size: 37888 | Author: 袁玉佳 | Hits:

[SCM] Counter

Description: 飞思卡尔单片机MC9SDG128B的计数器源程序，用于速度测量中脉冲个数统计，可以实现速度测量，路程测量等。-Freescale' s single-chip counters MC9SDG128B source for the pulse velocity measurement in the number of statistics, can achieve the speed measurement, distance measurement.
Platform: | Size: 303104 | Author: leeki | Hits:

[Software Engineering] VHDL

Description: 在电子技术中，频率是最基本的参数之一，又与许多电参量的测量方案、测量结果都有十分密切的关系，因此频率的测量就显得更为重要。测量频率的方法有多种,其中电子计数器测量频率具有精度高、使用方便、测量迅速，以及便于实现测量过程自动化等优点，是频率测量的重要手段之一。在本次毕业设计中我们选择使用单片机来制作数字频率计，并在实际制作中采用了直接测频法。利用延时产生的时基门控信号来控制闸门，通过在单位时间内计数器记录下的脉冲个数计算出输入信号的频率，最终送入LCD中显示。这样制作出来的频率计不仅可以满足设计题目的参数要求，而且具有了单片机的稳定性和成熟性，且控制能力强，是一种低成本，高可靠的设计方案。-In electronic technology, the frequency is one of the most basic parameters, but also with a number of electrical parameters of the measurement program, the measurement results have a very close relationship between the frequency of measurement, therefore it is even more important. Measurement of the frequency of a number of means, electronic measurement of the frequency counter with high precision, easy to use, rapid measurement, and measurement is easy to realize the advantages of process automation is an important means of measuring the frequency of one. Graduates in this design we have chosen to make use of single-chip digital frequency meter, and used in the actual production of a direct frequency measurement method. Delay arising from the use of gated time-base signal to control the gate time in units of the pulse counter to record the number of calculated frequency of the input signal, and ultimately into the LCD display. This produced not only the frequency of the parameters to
Platform: | Size: 220160 | Author: 张林锋 | Hits:

[SCM] dingshijishu

Description: pic单片机定时器和计数器的初始化程序，定时器0定时100ms，计数器T1计数外部脉冲个数，查寻方式-Single-chip timers and counters pic initialization procedure, Timer 0 Timing 100ms, external pulse counter counts the number of T1, search methods
Platform: | Size: 1024 | Author: 张吉卫 | Hits:

[Other] Pulsecount

Description: 脉冲计数，脉冲输入，脉冲上跳沿计数器加一，周期脉冲输入-Pulse count, pulse input, pulse on the jump along the counter plus one cycle pulse input
Platform: | Size: 1024 | Author: sam | Hits:

[Windows Develop] pulse_counter

Description: AVR MEGA8 Pulse Counter Proteus
Platform: | Size: 47104 | Author: starplus | Hits:

[Embeded-SCM Develop] pulsecounter6

Description: counter pulse embedded
Platform: | Size: 22528 | Author: nguyen | Hits:

[VHDL-FPGA-Verilog] Count

Description: 基于FPGA图形方法的同步模231计数器（设秒脉冲已给） -Graphical method based on the synchronous FPGA module 231 counter (pulse has been set up to)
Platform: | Size: 18432 | Author: david | Hits:

[SCM] temperature

Description: 此设计以单片机STC89C51为核心，由声音传感器采集脉搏信号，经过LM324前置放大电路、滤波电路和比较电路后得到与脉搏相关的脉冲信号，将该脉冲信号作为定时/计数器T1中断信号交由单片机进行脉冲周期的计算，T0做定时器。然后得出每分钟的脉搏搏动次数(即心率)，并将结果1602LCD上显示心率。在对人体脉搏检测时，具有检错排错的功能。若出现误操作（如不小心移动时产生的噪声）造成检测到的心跳次数不正确的结果，所以在程序中检测时间到达第5秒时，先对其进行计算，若结果超出正常范围则自动返回重新检测，直至结果正确，再继续检测5秒，最终由单片机计算出结果。在测量数据超过正常范围(如大于120次／min或小于45次／min)时自动重新开始检测。-Single-chip STC89C51 this design as the core, by the sound pulse sensor signal acquisition, the LM324 preamp circuit, filter circuit and compare the circuit to be associated with the pulse of the pulse signal, the pulse signal as the timer/counter interrupt signal cross-T1 single-chip pulse by calculating the cycle, T0 timer so.And then concludes that the pulse per minute pulse frequency (ie heart rate), and the results show 1602LCD heart rate. Pulse detected in the human body when debugging with the function of error. If misoperation (such as careless move noise) to detect the heartbeat caused by an incorrect number of results, so in the process of testing the time taken to reach the first five seconds, the first of its calculation,If the results exceed the normal range will automatically return to re-testing until the results of the right to continue testing for 5 seconds, the final results calculated by the single chip. In the measurement data over the normal range (for example, m
Platform: | Size: 1024 | Author: 郑雄 | Hits:
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