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[source in ebook] RSencode

Description: 包含RS（10，8）的verilog源程序，加法器的verilog源程序，卷积码的verilog源程序-Contains RS (10,8) of the Verilog source code, the Verilog source code adder, convolution of the Verilog source code
Platform: | Size: 1024 | Author: bai | Hits:

[VHDL-FPGA-Verilog] Convolution

Description:
Platform: | Size: 104448 | Author: 龚阳 | Hits:

[Communication] conv_vhdl

Description: 用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
Platform: | Size: 1024 | Author: 吴雪 | Hits:

[ActiveX/DCOM/ATL] prepha_conj

Description: 本代码用VHDL实现了复数的卷积，也许对你会有用-this code written by VHDL completes the convolution of complex numbers,which may be quite helpful to you.
Platform: | Size: 1024 | Author: 王远路 | Hits:

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