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[Other resource] VHDL-ysw

Description: 基于CPLD的棋类比赛计时时钟,第一个CNT60实现秒钟计时功能，第二个CNT60实现分钟的计时功能，CTT3完成两小时的计时功能。秒钟计时模块的进位端和开关K1相与提供分钟的计时模块使能，当秒种计时模块计时到59时向分种计时模块进位，同时自己清零。同理分种计时模块到59时向CTT3小时计时模块进位，到1小时59分59秒时，全部清零。同时，开关K1可以在两小时内暂停秒钟计时模块，分钟计时模块和小时计时模块。各模块的VHDL语言描述如下：-CPLD-based time clock chess competitions, a CNT60 achieve seconds timing, CNT60 second minute of time to achieve functional, CTT3 completion of the two-hour time function. Module seconds into time - and-switch K1 phase minutes for a time module can be enabled When seconds time to time module to the 59 minute time rounding module, reset themselves. Similarly minute time module to the 59-hour time CTT3 module rounding to 1 hour 59 minutes 59 seconds, reset all. Meanwhile, switches K1 can be suspended within two hours time module seconds, minutes and hours of time metering module module. The module VHDL is described as follows :
Platform: | Size: 2716 | Author: 杨仕伟 | Hits:

[Other] cnt60

Description: 同步计数器和异步计数器在设计时有哪些区别？试用　六进制计数器和一个十进制计数器构成一个六十进制同步计数器。-synchronous and asynchronous counter counter in the design these differences? 6 probation and 229 counters constitute a decimal counter a six decimal synchronous counter.
Platform: | Size: 848 | Author: sunqionghui | Hits:

[Other resource] CNT60

Description: 60进制加法器 本人自己编的，已通过老师检验，如有不足之处请多多指教
Platform: | Size: 120287 | Author: philin | Hits:

[Other] cnt60

Description: 同步计数器和异步计数器在设计时有哪些区别？试用　六进制计数器和一个十进制计数器构成一个六十进制同步计数器。-synchronous and asynchronous counter counter in the design these differences? 6 probation and 229 counters constitute a decimal counter a six decimal synchronous counter.
Platform: | Size: 1024 | Author: sunqionghui | Hits:

[VHDL-FPGA-Verilog] CNT60

Description: 60进制加法器 本人自己编的，已通过老师检验，如有不足之处请多多指教-60 hexadecimal adder I own, and has passed the teachers examination, any inadequacies in the exhibitions, please
Platform: | Size: 119808 | Author: philin | Hits:

[Linux-Unix] timingsystem

Description: 综合计时系统的 计秒模块 以及 计秒模块 调整控制电路 显示译码电路-Integrated timing system, the seconds and the seconds the module CNT60 adjust the control circuit module display decoder
Platform: | Size: 242688 | Author: Linkin | Hits:

[VHDL-FPGA-Verilog] cnt60

Description: de2开发板上的一个小程序 模60的计数器/分频器-de2 board developed a small program module 60 of the counter/divider
Platform: | Size: 263168 | Author: 李驰 | Hits:

[VHDL-FPGA-Verilog] cnt60

Description: 60进制计数器,（由一六进制和十进制连线组成）-60 binary counter (hexadecimal and decimal by a connection form)
Platform: | Size: 198656 | Author: 伍利衡 | Hits:

[Other] cnt60

Description: 通过简单的VHDL编辑的倒计时60秒，仅提供参考，如有不妥，请高手指正！-Countdown 60 seconds through a simple VHDL editor, only provide a reference, if wrong, master correction!
Platform: | Size: 1024 | Author: 赵盖 | Hits:

[VHDL-FPGA-Verilog] cnt60

Description: vhdl数字钟，有校时校分整点报时的基本功能-vhdl digital clock school, the school divided the whole point timekeeping function
Platform: | Size: 262144 | Author: ylh | Hits:

[ISAPI-IE] CNT60

Description: 六十进制计数器，显示0到60.可以用数码管显示。-Six decimal counter 0-60 can use the digital display.
Platform: | Size: 2048 | Author: mashasha | Hits:

[VHDL-FPGA-Verilog] CNT60

Description: 用VHDL设计了60的计数器，并用波形仿真验证了其功能-Design with VHDL counter 60, and a waveform simulation to verify its functionality
Platform: | Size: 375808 | Author: zhugege | Hits:

[VHDL-FPGA-Verilog] cnt60

Description: 60秒加一计数器，实现0到59秒计时。可以参照此例编写一个FPGA时钟，代码用VHDL编写。开发环境为quertues ii9.1.-60 seconds with a counter, to achieve 0 to 59 seconds. Can refer to this case to write a FPGA clock, the code written in VHDL. Development environment for quertues ii9.1.
Platform: | Size: 172032 | Author: Ronge | Hits:

[VHDL-FPGA-Verilog] cnt60

Description: 60计数器，管脚已经锁定，编译下载即可，二位60计数器-60 counter
Platform: | Size: 182272 | Author: 武千魄 | Hits:

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