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Description: 利用VHDL语言设计的数字钟,能进行正常的时、分、秒计时功能，分别由6个数码管显示24h、60min、60s
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Size: 146484 |
Author: 可爱 |
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Description: 利用VHDL语言设计的数字钟,能进行正常的时、分、秒计时功能，分别由6个数码管显示24h、60min、60s-The use of VHDL language design digital clock, can be a normal hour, minute, second timing function, respectively, by 6 digital tube display 24h, 60min, 60s
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Size: 146432 |
Author: 可爱 |
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Description: 采用自顶向下设计方法，由秒计数模块、分计数模块、时计数模块、时间设置模块和译码模块五部分组成。-Using top-down design methodology, from the second counter module, sub-counting module, when the counting module, time setting module and decoding module of five parts.
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Size: 5120 |
Author: hao |
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Description: 电子时钟VHDL程序与仿真,详细介绍了设计的整个阶段，验证过，可以运行的。-Electronic clock and simulation of VHDL procedures, detailed design of the stage, verified, you can run.
Platform: |
Size: 63488 |
Author: 王涛 |
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Description: clockVHDL数字钟模块CNT60_2 该模块为60进制计数器，计时输出为秒的数值，在计时到59时送出进位信号CO,因为硬件有延时，所以模块CNT60_2在此模块变为00时加1，符合实际。-clockVHDLCapable of normal hours, minutes, seconds, chronograph functions, six digital tube display 24h, 60min, 60s.
Sa key is pressed, the timer increments rapidly, and 24h cycle timing back to 00 full 23h
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Size: 1024 |
Author: 铁笼 |
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