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[Other resourceCcs_experiment

Description: CCS调试实验文件夹下共有9个文件夹,使用时先将以下所有文件夹拷贝到ti\\myprojects下。 一、Hello1 CCS使用实验 二、Volume1 CCS使用实验 三、chenfa 小数乘法实验 四、chufa 小数除法实验 五、Diir IIR滤波器实验 六、Fir FIR滤波器实验 七、Fft0 ffT程序实验 八、Sinbo 信号产生实验 九、LMS 自适应滤波器实验 -CCS debugging experimental folder there were nine folder, first use all of the following folders to copy ti \\ myprojects under. 1, Hello1 two experimental use CCS, CCS Volume1 three experimental use, chenfa experimental four decimal multiplication, division chufa decimal experimental 5, Diir IIR filter experimental 6, Fir FIR filter experiment 7, Fft0 ffT eight experimental procedures, Sinbo signal experiment 9, LMS adaptive filter experiment
Platform: | Size: 340001 | Author: lvxinhua | Hits:

[Other resourcechufa

Description: 一个简单的除法器,可以供各位参考!
Platform: | Size: 911 | Author: YjLiu | Hits:

[DSP programCcs_experiment

Description: CCS调试实验文件夹下共有9个文件夹,使用时先将以下所有文件夹拷贝到ti\myprojects下。 一、Hello1 CCS使用实验 二、Volume1 CCS使用实验 三、chenfa 小数乘法实验 四、chufa 小数除法实验 五、Diir IIR滤波器实验 六、Fir FIR滤波器实验 七、Fft0 ffT程序实验 八、Sinbo 信号产生实验 九、LMS 自适应滤波器实验 -CCS debugging experimental folder there were nine folder, first use all of the following folders to copy ti \ myprojects under. 1, Hello1 two experimental use CCS, CCS Volume1 three experimental use, chenfa experimental four decimal multiplication, division chufa decimal experimental 5, Diir IIR filter experimental 6, Fir FIR filter experiment 7, Fft0 ffT eight experimental procedures, Sinbo signal experiment 9, LMS adaptive filter experiment
Platform: | Size: 339968 | Author: | Hits:

[VHDL-FPGA-Verilogchufa

Description: 一个简单的除法器,可以供各位参考!-A simple division, you can for your reference!
Platform: | Size: 1024 | Author: YjLiu | Hits:

[Otherchufa

Description: 化简分数到最简 目前只支持质数小于10000的情况-Simplification of scores to the most Jane prime number currently only supports the case of less than 10000
Platform: | Size: 1024 | Author: halforc | Hits:

[Other Embeded programchufa

Description: 超声波测距器 * * 采用 AT89C52 12MHZ晶振 * * 采用共阳LED显示器 LRM 2004.03.18 * ******************************************** 测距范围7CM-11M,堆栈在4FH以上,20H用于标志 显示缓冲单元在40H-43H,使用内存44H、45H、46H用于计算距离-Ultrasonic range-finder using AT89C52 12MHZ**** to adopt a total crystal Yang LED display LRM 2004.03.18********************************************* ranging scope of 7CM-11M, the stack in 4FH above, 20H for buffer unit showed signs in the 40H-43H, the use of memory 44H, 45H, 46H for calculating the distance
Platform: | Size: 7168 | Author: 囧明 | Hits:

[VHDL-FPGA-Verilogchufaqi

Description: 时序电路是指它的输出不仅取决于当时的输入,而且也取决于过去的输入,即过去输入不同,则在当前的情况下,输出也可能不同。-Sequential circuit is the output depends not only on its input at that time, but also on past input, that is different from the last input, then in the current circumstances, the output also may be different.
Platform: | Size: 2048 | Author: hellen | Hits:

[CSharpchufa

Description: 这是一个除法程序,游兴趣的朋友可以瞧瞧,具体功能看了就知道啦-not sure,if you like you can have a look!
Platform: | Size: 178176 | Author: 蔡志刚 | Hits:

[Windows Developchufa

Description: 汇编语言 除法 我收集的 4个-Division assembly language, I collected four
Platform: | Size: 10240 | Author: 张志刚 | Hits:

[Othercepin

Description: 用于测试波形的频率,从10-10Mhz可测,对任意波形可测。-it is based on FPGA and shimite chufa ,and the frequency of the desired wave is gotten.
Platform: | Size: 2430976 | Author: zhaomei | Hits:

[Otherchufa

Description: 使用VHDL编写的除法程序,当然是采用的分数形式,小数点的除法还没有实现。-Division programs written using VHDL, of course, use the Fraction, decimal point of division has not been achieved.
Platform: | Size: 1024 | Author: 张见平 | Hits:

[SCMchufa

Description: 51单片机,汇编语言。双字节二进制无符号数除法。可以留作程序库使用哦。-51 microcontroller, assembly language. Double-byte unsigned binary division. Can be reserved for library use, oh.
Platform: | Size: 1024 | Author: doeryhn | Hits:

[VHDL-FPGA-Verilogchufa

Description: 二进制除法实现,可实现四位二进制的除法运算-Binary division to achieve, enabling four binary division
Platform: | Size: 1024 | Author: 宋关龙 | Hits:

[VHDL-FPGA-Verilogchufa

Description: 描述一个4位除法器,实现,包含源代码,及其其它说明-Describe a 4-bit divider, and includes source code, and other instructions
Platform: | Size: 303104 | Author: liuhuacheng | Hits:

[VHDL-FPGA-Verilogchufa

Description: 四位有符号数字除法 用于basys2板子-divider divider for basys2 sjtu
Platform: | Size: 4096 | Author: 周晓辰 | Hits:

[VHDL-FPGA-Verilogchufa

Description: 用VHDL设计的四位除法器,可以实现四位二进制数的除法操作-Four divider with VHDL design, you can achieve the four binary division operation
Platform: | Size: 1024 | Author: 陈峰 | Hits:

[LabViewchufa

Description: (2) 发生一个值为0.0~10.0之间的随机数,并除以一个在前面板中输入的数。如果输入的数为0,则点亮LED,提示除数为0时,除法无效。-(2) a value of 0.0 to 5.0 occurred between random numbers and dividing by a number entered in the front panel. If the input is 0, then lit LED, prompted the divisor is 0, the division is invalid.
Platform: | Size: 15360 | Author: eric | Hits:

[VHDL-FPGA-Verilogchufa

Description: 开放式实验,CPU实验除法器,一个简单的除法器-Open experiment, CPU test divider, a simple divider
Platform: | Size: 214016 | Author: 痴心 | Hits:

[Multimedia Developchufa

Description: 化简分数到最简目前只支持质数小于10000的情况-Simplification of scores to the most Jane prime number currently only supports the case of less than 10000
Platform: | Size: 1024 | Author: keng9916406 | Hits:

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