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Description: 完成ccitt crc的校验。针对hdlc协议控制器编写的crc校验模块。通过了仿真测试-Ccitt crc checksum completed. HDLC protocol controller for the preparation of the CRC checksum module. Through the simulation test
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Description: 16位的CRC校验函数包。符合ccitt标准，查表法校验，速度快。节省CPU时间。值得一看！-16 The CRC checksum function package. Consistent with the CCITT standards, look-up table method validation, fast. Save CPU time. Worth a visit!
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Size: 1024 |
Author: cumt |
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Description: 数字基带信号的传输是数字通信系统的重要组成部分。在数字通信中，有些场合可不经过载波调制和解调过程，而对基带信号进行直接传输。采用AMI码的信号交替反转，有可能出现四连零现象，这不利于接收端的定时信号提取。而HDB3码因其无直流成份、低频成份少和连0个数最多不超过三个等特点，而对定时信号的恢复十分有利，并已成为CCITT协会推荐使用的基带传输码型之一。为此，本文利用VHDL语言对数据传输系统中的HDB3编码器进行了设计。-Digital baseband signal transmission is an important digital communication system components. In digital communications, some occasions may, after modulation and demodulation process, and on the base-band signals transmitted directly. AMI code using the turn signal inversion, there may be zero Silian phenomenon, which is not conducive to the receiving end of the timing signal extraction. HDB3 code and its non-DC components, and even less low-frequency components of 0 up to more than three the number of characteristics such as timing signals for the recovery of very favorable, and the Association has become the CCITT recommended base-band transmission-type, one code. In this paper, the use of VHDL language in the data transmission system HDB3 encoder has been designed.
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Size: 108544 |
Author: shashou |
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Description: CRC-16 VHDL Source Code
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Size: 164864 |
Author: kobin |
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Description: CCITT Parallel CRC 16-bit
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Size: 1024 |
Author: timngo |
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Description: E1 Framer/Deframer,E1 framer Deframer core implements CCITT (ITU) recommedations G.704,G.706 and G.732 for 30 channel multiplexed E1 stream at 2.048Mbps rate.
Note:This project is part of the OpenStacks initiative at the Telecom Software Laboratory, Electrical Engineering Department / Bharti School of Telecommunication Technology & Management. The initiative is founded and led by Dr.Subrat Kar (subrat@ee.iitd.ac.in) at the Department of Electrical Engineering, IIT Delhi-E1 Framer/Deframer, E1 framer Deframer core implements CCITT (ITU) recommedations G.704, G.706 and G.732 for 30 channel multiplexed E1 stream at 2.048Mbps rate. Note: This project is part of the OpenStacks initiative at the Telecom Software Laboratory, Electrical Engineering Department/Bharti School of Telecommunication Technology & Management. The initiative is founded and led by Dr.Subrat Kar (subrat@ee.iitd.ac.in) at the Department of Electrical Engineering, IIT Delhi
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Author: xiao |
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Description: 循环冗余校验 CRC 的算法分析和程序实现。通信的目的是要把信息及时可靠地传送给对方，因此要求一个通信系统传输消息必须可靠与快速，在数字通信系统中可靠与快速往往是一对矛盾。为了解决可靠性，通信系统都采用了差错控制。本文详细介绍了循环冗余校验CRC（Cyclic Redundancy Check）的差错控制原理及其算法实现-Cyclic Redundancy Check
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Size: 106496 |
Author: 朱红 |
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Description: 数字基带信号的传输是数字通信系统的重要组成部分。在数字通信中，有些场合可不经过载波调制和解调过程，而对基带信号进行直接传输。采用AMI码的信号交替反转，有可能出现四连零现象，这不利于接收端的定时信号提取。而HDB3码因其无直流成份、低频成份少和连0个数最多不超过三个等特点，而对定时信号的恢复十分有利，并已成为CCITT协会推荐使用的基带传输码型之一。为此，本文利用VHDL语言对数据传输系统中的HDB3编码器进行了设计。
基于达到达到达到的信号发生器的源程序-Digital baseband signal transmission is a digital communications system, an important component. In digital communication, there are some occasions, may from time through the carrier modulation and demodulation process, the base-band signal for direct transmission. AMI code signal using alternating inversion, there may be four to zero with the phenomenon, which is not conducive to the receiving end of the timing signal extraction. The HDB3 code because of its non-DC components, low-frequency components, and even a small number of 0 up to more than three characteristics, while the timing signal recovery is very favorable, and has become CCITT Association recommended one of baseband transmission pattern. In this paper the use of VHDL language for data transmission system in the HDB3 encoder has been designed. Based on the signal generator to achieve to reach to reach the source
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Size: 3072 |
Author: 成风 |
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Description: -- crc.vhd
-- Used for calculation of CRC16-CCITT
-- Intended use is as custom peripheral for Nios processor
-- When address is logic 0 =>
-- Internal CRC register is initialised with write_data value
-- When address is logic 1 =>
-- CRC calulation is updated based on input word on write_data
-- CRC result is obtained by reading any address
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Size: 1024 |
Author: Jan Petak |
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Description: 由于altera公司的CRC生成和校验模块不支持本系统使用的Cyclone IV E系列FPGA，因此本文独立设计了CRC模块。该模块的接口与altera公司的CRC模块接口基本一致，能够对16位输入的数据流进行CRC校验码生成和校验。本文采用CRC-CCITT生成项，其表达式为：X16+X12+X5+X0。本模块需要startp信号及endp信号指示数据传输的起始及结束。本模块采用状态机设计，对于数据头和数据尾分别由不同的状态来处理。在本模块中，使用了for循环，这会消耗较多的FPGA资源，但暂时任未发现其他改进的方法。-Because altera company' s CRC generation and checking modules do not support the use of the system Cyclone IV E series FPGA, so this independent design of the CRC module. The module' s interface with the CRC module interface altera' s basically the same, capable of 16-bit input data stream of CRC generation and checking. In this paper, CRC-CCITT generation entry, its expression is: X16+ X12+ X5+ X0. This module requires startp signal and endp signal indicating the start and end of data transmission. This module is a state machine design, and data for the end of the first data were handled by different states. In this module, use the for loop, which consumes more FPGA resources, but temporarily did not find any other ways to improve.
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Size: 4096 |
Author: 陈建 |
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