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[Data structs] BCH

Description: 一个解码的类，常用在条形码的解码中，是老外写的比较实用-a decoder category, commonly used in bar code decoding, the foreigner is more practical writing
Platform: | Size: 3072 | Author: 刘怀国 | Hits:

[VHDL-FPGA-Verilog] crc3321

Description: CRC循环校验码的VERILOG源文件，在MODELSIM下的一个工程。-Cyclic Check Code VERILOG source, the MODELSIM of a project.
Platform: | Size: 26624 | Author: 刘仪 | Hits:

[source in ebook] BCHandRS

Description: 一些纠错编码的c程序实现，包括bch码，rs码，均已调试通过-some of the c-correction coding program, including BCH code, rs codes have been adopted Debugging
Platform: | Size: 842752 | Author: 张华 | Hits:

[VHDL-FPGA-Verilog] bch_encoder_decoder

Description: bch encoder+decoder 源代码，Flash控制器，通讯都需要用到哦-bch encoder+ decoder source code, Flash controller, communications are needed Oh
Platform: | Size: 136192 | Author: linchan | Hits:

[Windows Develop] BCH_Decoder72

Description: BCH代码，采用VHDL实现，能够实现纠错，带有波形。-BCH code, the use of VHDL implementation, be able to achieve error correction with waveform.
Platform: | Size: 206848 | Author: daisy | Hits:

[Communication] BCHbch

Description: BCH编码 实现BCH信道编码功能 实现BCH信道编码功能-BCH code BCH code BCH code BCH code BCH code BCH code BCH code
Platform: | Size: 933888 | Author: p2pover | Hits:

[Streaming Mpeg4] rs_encode

Description: 这是用verilog编写的RS（204，188）代码，适用于数字电视的BCH编码过程。-This is the verilog prepared using RS (204,188) code, the application of digital television in the course of the BCH code.
Platform: | Size: 2048 | Author: 蕊宫獍雪 | Hits:

[VHDL-FPGA-Verilog] viterbi_for_bch

Description: Viterbi based trellis decoder for (7,4) - binary BCH code-Viterbi based trellis decoder for (7,4)- binary BCH code
Platform: | Size: 1024 | Author: shahifaqeer | Hits:

[VHDL-FPGA-Verilog] Verilog_for_BCH

Description: 使用verilog语言实现BCH编码，用于通信信道编码-Using verilog language implementation BCH coding, channel coding for communication
Platform: | Size: 9465856 | Author: 咕嘟大树 | Hits:

[VHDL-FPGA-Verilog] bch_encode

Description: this bch encoder verilog code-this is bch encoder verilog code
Platform: | Size: 2048 | Author: rakhi | Hits:

[matlab] BCH[31-16]-with-BPSK-MFSK

Description: comperation of performance of BCH [31 16] code with BPSK and MFSK
Platform: | Size: 12288 | Author: kantaria | Hits:

[VHDL-FPGA-Verilog] BCH_EN

Description: 基于FPGA的GPS/BD信号发生器中BCH编码发生器模块，使用verilog编写- FPGA-based GPS/BD signal generator BCH code generator module, using verilog write
Platform: | Size: 4570112 | Author: 刘先生 | Hits:

[VHDL-FPGA-Verilog] BCH_VLSI

Description: 使用HLS完成BCH编码的运算通路的设计，纯组合逻辑，对于65nm工艺可跑上1GHz。已经组合逻辑分为了多个部分，可在每一个部分之间插流水线。 附上可综合的纯RTL Code以及C++代码，以及Modelsim仿真。 可通过我的优化选项来学习如何优化HLS工具生产的代码。(BCH Encoder realized using HLS tool. Combinational logic.)
Platform: | Size: 14505984 | Author: 蔡宇杰 | Hits:

[VHDL-FPGA-Verilog] bch_verilog-master

Description: BCH code Open Source
Platform: | Size: 63488 | Author: sunili | Hits:

[VHDL-FPGA-Verilog] 2bit_ecc

Description: 基于BCH码的ECC纠错算法，可纠错2位错误码，供参考(Based on BCH code ECC error correction algorithm, two error codes can be corrected for reference.)
Platform: | Size: 24576 | Author: 一粒尘埃 | Hits:

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