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[Other resource] BCDADD

Description: 本程序完成多个BCD码加法,并完成到十进制裁转换-completion of the procedures BCD adder, and complete the conversion to decimal Conference
Platform: | Size: 1904 | Author: 王永良 | Hits:

[VHDL-FPGA-Verilog] verlog_basic

Description: 用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器，乘法器，除法器，多路选择器，二进制转BCD码，加法器，减法器等等。-verlog used some language addendum to the basic experiment, which is suitable for FPGA/CPLD beginners. Including eight priority encoder, multipliers, dividers, multi-path selectors, binary switch BCD, adder, subtraction, and so on.
Platform: | Size: 1004544 | Author: leolili | Hits:

[MPI] add_16_bcd

Description: 此程序采用VHDL语言，完成在16位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的16位二进制加法器-This procedure using VHDL language, completed in 16-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 16 binary adder
Platform: | Size: 1024 | Author: 韩善华 | Hits:

[VHDL-FPGA-Verilog] add_32_bcd

Description: 此程序采用VHDL语言，完成在32位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的32位二进制加法器-This procedure using VHDL language, completed in 32-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 32 binary adder
Platform: | Size: 1024 | Author: 韩善华 | Hits:

[VHDL-FPGA-Verilog] bcd2

Description: 二位BCD码加法器 加数与被加数都是2进制。输出和为10进制。 结果显示在LED上。-Code 2 BCD adder with the summand summand are 2 hexadecimal. Output and 10 hexadecimal. The results showed that in the LED on.
Platform: | Size: 8192 | Author: 刘锐 | Hits:

[assembly language] bcd

Description: 实现一位BCD码的加法，并且带有进位。还可以利用逻辑电路实现此功能。-Code to achieve a BCD adder, and a binary. Logic circuits can also be used to achieve this functionality.
Platform: | Size: 3072 | Author: 廉子 | Hits:

[VHDL-FPGA-Verilog] bcd_adder

Description: verilog code for bcd adder
Platform: | Size: 10240 | Author: sandeep | Hits:

[MPI] Parallel-adder

Description: 并行加法器是一种数位电路，其可进行数字的加法计算。在现代的电脑中，加法器存在于算术逻辑单元（ALU）之中。 加法器可以用来表示各种数值，如：BCD、加三码，主要的加法器是以二进制作运算。-Parallel adder is a digital circuit, which can be calculated the number of addition. In the modern computer, adder exists in the arithmetic logic unit (ALU) into. Adder can be used to express a variety of values, such as: BCD, plus three yards, the major is based on a binary adder for computing.
Platform: | Size: 3072 | Author: jlz | Hits:

[File Format] bitbcdadder

Description: bcd adder implemented in three models of vhdl
Platform: | Size: 59392 | Author: sathishkumar | Hits:

[VHDL-FPGA-Verilog] BCD8

Description: BCD码十进制8位加法器，采用超前进位的方法-8-bit decimal BCD adder yards, using look-ahead approach
Platform: | Size: 1024 | Author: 刘骁明 | Hits:

[SCM] Advanced_Adders

Description: Advanced topic on adders including: Carry Look Ahead Adder, Binary Parallel Adder/Subtractor, BCD adder circuit, Binary mutiplier circuit.
Platform: | Size: 338944 | Author: Bao | Hits:

[Software Engineering] bcd-adder

Description: its bcd progrrame in mentor graphics
Platform: | Size: 3072 | Author: sreenivasulu | Hits:

[Software Engineering] A-New-Reversible-Design-of-BCD-Adder

Description: Designing a BCD adder
Platform: | Size: 104448 | Author: Anand | Hits:

[VHDL-FPGA-Verilog] A-Novel-Reversible-BCD-Adder-For-Nanotechnology-B

Description: A Novel Reversible BCD Adder For Nanotechnology Based System
Platform: | Size: 190464 | Author: Christoffer | Hits:

[VHDL-FPGA-Verilog] Design-and-Optimization-of-Reversible-BCD-Adder-S

Description: Design and Optimization of Reversible BCD Adder-Subtractor Circuit
Platform: | Size: 78848 | Author: Christoffer | Hits:

[VHDL-FPGA-Verilog] Design-of-Optimized-Reversible-BCD-Adder-Subtract

Description: Design of Optimized Reversible BCD Adder-Subtractor 229
Platform: | Size: 790528 | Author: Christoffer | Hits:

[VHDL-FPGA-Verilog] Optimized-design-of-BCD-adder-and-Carry

Description: Optimized design of BCD adder and Carry
Platform: | Size: 174080 | Author: Christoffer | Hits:

[VHDL-FPGA-Verilog] Optimized-reversible-BCD-adder-using-new

Description: Optimized reversible BCD adder using new
Platform: | Size: 265216 | Author: Christoffer | Hits:

[VHDL-FPGA-Verilog] BCD-adder

Description: 用VHDL语言设计一个BCD码加法器，输入A[3..0]、B[3..0],输出为SUM[4..0]。-bcd adder
Platform: | Size: 3072 | Author: 王小雨 | Hits:

[VHDL-FPGA-Verilog] A-New-Reversible-Design-of-BCD-Adder

Description: This a good implementation of reversible adder-This is a good implementation of reversible adder
Platform: | Size: 104448 | Author: Rishabh Bansal | Hits:
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