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Description: library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PL_auto1 is
port ( clk:in std_logic; --系统时钟
set,get,sel,finish: in std_logic; --设定、买、选择、完成信号
coin0,coin1: in std_logic; --5角硬币、1元硬币
price,quantity :in std_logic_vector(3 downto 0); --价格、数量数据
item0 , act:out std_logic_vector(3 downto 0); --显示、开关信号
y0,y1 :out std_logic_vector(6 downto 0); --钱数、商品数量显示数据
act10,act5 :out std_logic); --1元硬币、5角硬币
end PL_auto1;
architecture behav of PL_auto1 is
type ram_type is array(3 downto 0)of std_logic_vector(7 downto 0);
signal ram :ram_type; --定义RAM
signal item: std_logic_vector(1 downto 0); --商品种类
signal coin: std_logic_vector(3 downto 0); --币数计数器
signal pri,qua:std_logic_vector(3 downto 0); --商品单价、数量
signal clk1: std_logic; --控制系统的时钟信号
begin
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Size: 204288 |
Author: niuyuanlai@163.com |
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Description: 【经典设计】VHDL源代码下载～～
其中经典的设计有：【自动售货机】、【电子钟】、【红绿灯交通信号系统】、【步进电机定位控制系统】、【直流电机速度控制系统】、【计算器】、【点阵列LED显示控制系统】
基本数字逻辑设计有：【锁存器】、【多路选择器】、【三态门】、【双向输入|输出端口】、【内部（缓冲）信号】、【编码转换】、【加法器】、【编码器/译码器】、【4位乘法器】、【只读存储器】、【RSFF触发器】、【DFF触发器】、【JKFF触发器】、【计数器】、【分频器】、【寄存器】、【状态机】
- [ Classics design ] the VHDL source code downloads ~ ~ classics
the design to include: [ Vending machine ], [ electron clock ], [
traffic light traffic signal system ], [ step of 杩涚數 machine
localization control system ], [ direct current machine speed control
system ], [ calculator ], [ array LED display control system ] the
basic numeral logical design includes: [ Latch ], [ multichannel
selector ], [ 涓夋
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Size: 44032 |
Author: senkong |
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Description: 用C51实现的拼音输入法,这是改写的网友 embuffalo、独步上载在www.21ic.com自由发布区的由张凯原作的51上的拼音输入法程序。
原作使用了一个二维数组用以查表，我认为这样比较的浪费空间，而且每个字表的索引地址要手工输入，效率不高。所以我用结构体将其改写了一下。就是大家现在看到的这个。
因为代码比较的大，共有6,000多汉字，这样就得要12,000 byte来存放GB内码，所以也是没办法的 :-(
编译结果约为3000h,因为大部分是索引表，代码优化几乎无效。
在Keil C里仿真芯片选用的是华邦的W77E58，它有32k ROM, 256B on-chip RAM, 1K on-chip SRAM (用DPTR1指针寻址,相当于有1K的片上xdata)。条件有限，没有上片试验，仿真而已。
打算将其移植到AVR上，但CodeAVRC与IAR EC++在结构体、指针的定义使用上似乎与C51不太一样，现在还未搞定。还希望在这方面有经验的网友能给予指导。-C51 with the Pinyin input method, which is rewritten netizens embuffalo. Unrivaled www.21ic.com available in the free publication of the original work by Kai-51 on the Pinyin input method procedures . Appreciate the use of a two-dimensional array for the look-up table, I think this is a waste of space. Each of the characters but the index table to manually input address, efficiency is not high. I use the structure to rewrite a bit. We see now is this. Because the code comparison, a total of 6, more than 000 Chinese characters, this must be 12, byte to store 000 GB code, is not the way to compile results :-( about 3000h. because most of the index table. Code Optimization almost ineffective. Keil in the C simulation uses the chip in W77E58 Winbond, It has 32 k ROM 256B on-chip RAM, 1K on-chi
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Size: 14336 |
Author: Jawen |
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Description: 关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
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Size: 179200 |
Author: 李中伟 |
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Description: 利用超高速硬件描述语言(VHDL)在现场可编程逻辑门阵列(FPGA)上编程实现的纯数字式等精度频率计，不但具有较高的测量精度，而且其测量精度不会随着被测信号频率的降低而下降。为了实现对任意信号进行频率测量，在前端输入加整形电路即可。-use ultra-high-speed Hardware Description Language (VHDL) in field programmable logic gate array (FPGA) series The way to achieve such pure digital frequency meter accuracy, not only with higher measurement accuracy, but not its measurement precision frequency signals measured with the decrease. In order to achieve the arbitrary measurement signal frequency, increase input in the front plastic circuit can be.
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Size: 30720 |
Author: 刘刚 |
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Description: 8点阵列LED显示屏的
VHDL扫描程序-8:00 Array LED display VHDL scanner
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Size: 1024 |
Author: ww |
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Description: 利用邻接矩阵的图广度优先遍历算法,
利用子指针数组的普通树前根遍历算法-The use of adjacency matrix of the graph breadth-first traversal algorithm, using sub-array pointer before the root of the general tree traversal algorithm
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Size: 11264 |
Author: 左 |
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Description: 基于SOC的线阵CCD图像采集单元设计.pdf-SOC based on the linear array CCD image acquisition unit design. Pdf
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Size: 506880 |
Author: 王剑雨 |
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Description: 本文主要讨论了使用EDA工具设计汉字滚动显示器的技术问题。文中首先描述了基于现场可编程门阵列（FPGA）的硬件电路；然后研究了在8×8LED发光二极管点阵上显示滚动汉字的原理，并给出了基于ALTERA的参数化模型库LPM描述其功能的VHDL语言程序设计；最后对使用EDA工具软件加工被显示数据文件的方法进行了讨论。-This paper mainly discusses the use of EDA tools for the design of Chinese characters scrolling display technology. First, the description based on field programmable gate array (FPGA) hardware circuit and then studied in the 8 × 8LED LED dot matrix display scroll principle characters, and gives ALTERA based on parameterized model library LPM Description its function in VHDL language programming Finally on the use of EDA software tools for processing data files being displayed method is discussed.
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Size: 185344 |
Author: wang |
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Description: 现场可编程逻辑门阵列在实时数字图像处理中的应用-Field-programmable gate array logic in real-time digital image processing
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Size: 159744 |
Author: 刘文娟 |
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Description: 智能天线自适应LMS算法，假设具有4个天线阵元。-Smart antenna adaptive LMS algorithm, the assumption that with four million antenna array.
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Size: 4096 |
Author: 黄虎 |
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Description: 用VHDL语言实现CCD图象采集系统，针对TCD1205线阵CCD传感器-Using VHDL language CCD image acquisition system for TCD1205 linear array CCD sensors
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Size: 8192 |
Author: xujingjing |
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Description: 在软件MAX+plus II环境中，设计了一台RISC模型机，具有以下功能：输入包含10个整数（无符号数）的数组M，按从小到大的顺序输出这10个数。-In terms of software MAX+ Plus II environment, the design model of a RISC machine, has the following features: input contains 10 integer (unsigned number) of the array M, according to the order from small to large number of the output of these 10.
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Size: 937984 |
Author: 陈自分 |
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Description: :针对现场可编程门阵列(FPGA)芯片的特点,研究FPGA中双向端口I/O的设计,同时给
出仿真初始化双向端口I/O的方法。采用这种双向端口的设计方法,选用Xilinx的Spartan2E芯片
设计一个多通道图像信号处理系统。-: For field programmable gate array (FPGA) chip features of FPGA in the bi-directional port I/O design, the simulation is initialized at the same time two-way port I/O method. Using this design method of two-way ports, optional Spartan2E the Xilinx chip to design a multi-channel image signal processing system.
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Size: 115712 |
Author: zhanyi |
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Description: 基于CPLD的光积分时间可调线阵CCD驱动电路设计-CPLD-based optical integration time adjustable linear array CCD Drive Circuit Design
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Size: 418816 |
Author: 赵晖 |
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Description: 摘 要：介绍了直接数字频率合成 (DDS) 技术的基本原理，给出了基于Altera公司FPGA器件的一个三相正弦信号发生器的设计方案，同时给出了其软件程序和仿真结果。仿真结果表明：该方法生成的三相正弦信号具有对称性好、波形失真小、频率精度高等优点，且输出频率可调。
关键词：直接数字频率合成；现场可编程门阵列；FPGA；三相正弦信号-Abstract: Direct Digital Synthesis (DDS) technology, the basic principles are given Altera-based FPGA devices the company a three-phase sinusoidal signal generator design program, at the same time give its software programs and simulation results. The simulation results show that: the method to generate three-phase sinusoidal signal with good symmetry, waveform distortion small, the frequency of high precision, and adjustable output frequency. Key words: direct digital synthesizer field programmable gate array FPGA three-phase sinusoidal signal
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Size: 101376 |
Author: 赵文 |
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Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型
化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了
三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
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Size: 546816 |
Author: John |
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Description: 麦克风阵列的TLS自适应波束形成算法仿真，麦克间距和输入信号带宽可调，通过调整参数达到需要的输出-TLS microphone array adaptive beamforming algorithm simulation, Mike spacing and input signal bandwidth is adjustable by adjusting the parameters to achieve the required output
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Size: 396288 |
Author: 萧球水 |
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Description: The concept of the Altera Nios II embedded processor implementation inside Field Programmable Gate Array [FPGA] of the CCD camera for the “Pi of the Sky” experiment is presented. The digital board of the CCD camera, its most important components, current implementation of firmware [VHDL] inside the FPGA and the role of external 8051 microcontroller is briefly described. The main goal of the presented work is to get rid of the external microcontroller and to design new system with Nios II processor built inside FPGA chip. Constraints for implementing the design into the existing camera boards are discussed. New possibilities offered by a larger FPGA for next generation of cameras are considered.-The concept of the Altera Nios II embedded processor implementation inside Field Programmable Gate Array [FPGA] of the CCD camera for the “Pi of the Sky” experiment is presented. The digital board of the CCD camera, its most important components, current implementation of firmware [VHDL] inside the FPGA and the role of external 8051 microcontroller is briefly described. The main goal of the presented work is to get rid of the external microcontroller and to design new system with Nios II processor built inside FPGA chip. Constraints for implementing the design into the existing camera boards are discussed. New possibilities offered by a larger FPGA for next generation of cameras are considered.
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Size: 1427456 |
Author: Francis Wu |
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Description: :文章针对目前数字信号处理中大量采用的快速傅立叶变换[FFT] 算法采用软件编程来处理的应用现状,在对FFT 算法进行
分析的基础上,给出了用FPGA[Field Programmable Gate Array] 实现的8 点32 位FFT 处理器方案,并得到了系统的仿真结果。
最后在Altera 公司FLEX10K系列FPGA 芯片上成功地实现了综合。-Based on the analysis of the FFT algorithm , a reasonable logic structure for a 8-point ,32- bit FFT processor is described and the simulating
result is given in this paper. The processor is implemented on the FLEX10Kfamily of FPGAs.
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Size: 220160 |
Author: 王晓 |
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