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Description: Arbiter.v verilog实现
三路请求,使用循环策略的仲裁器
含有看门狗电路-Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit
Platform: |
Size: 2048 |
Author: 夏虫 |
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Description: Arbiter unit includes client and server units.
Used for Arbitation of multipliers in Altera FPGA based project.
The code supports several multipliers and several clients with different priorities.-Arbiter unit includes client and server units.
Used for Arbitation of multipliers in Altera FPGA based project.
The code supports several multipliers and several clients with different priorities.
Platform: |
Size: 6144 |
Author: d0238 |
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Description: 一个自己用verilog写的路由仲裁器的程序,基于fpga。-Own use verilog to write a routing arbiter of the program, based on fpga.
Platform: |
Size: 35840 |
Author: DYP |
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Description: Round Robin priority arbiter
Platform: |
Size: 47104 |
Author: taso999
|
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Description: 带权重的优先级轮转算法的verilog实现(Verilog implementation of priority rotation algorithm with weight)
Platform: |
Size: 437248 |
Author: 鱼在在藻 |
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