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Description: 关于i2c master/slaver control 方面的技术资料 介绍其特色与使用方法-On the i2c master/slaver control of technical information on their characteristics and use
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Size: 111616 |
Author: gaoguoxin |
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Description: APB master verilog code
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Size: 1024 |
Author: Ajay |
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Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
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Size: 17408 |
Author: jinjin |
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Description: APB slave master uding verilog
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Size: 4096 |
Author: vivek |
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Description: APB 总线。可以实现单个数据在总机与从机之间的读写功能(This can achieve the read and write functions of a single data between the master and the slave .)
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Size: 1024 |
Author: zxppppppppp
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Description: ahb to apb master and slave
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Size: 3072 |
Author: Sheth |
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Description: ahb to apb master verification
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Size: 2403328 |
Author: Sheth |
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Description: 是基于apb总线下的timer外设的rtl代码，主要包括apb_timer的master逻辑verilog，以及相应的开发文档，包括寄存器的描述，功能特性等。(RTL code is based on timer peripheral under APB bus, which mainly includes master logic Verilog of apb_timer and corresponding development documents, including the description of registers, functional characteristics and so on.)
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Size: 67584 |
Author: megmand |
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Description: apb转i2c verilog 实现(APB bus interface to I2C bus interface)
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Size: 445440 |
Author: AyanamiC |
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