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[Other resource] cordic_v1.0.4

Description: Altera公司的CORDIC开发包，用Verilog编写的，安装在Quartus相同目录中，里面有详细的开发说明。
Platform: | Size: 1356409 | Author: YangJun | Hits:

[Post-TeleCom sofeware systems] cordic_v1.0.4

Description: Altera公司的CORDIC开发包，用Verilog编写的，安装在Quartus相同目录中，里面有详细的开发说明。-Altera
Platform: | Size: 1355776 | Author: YangJun | Hits:

[VHDL-FPGA-Verilog] cordiccos

Description: 改进的cordic算法的迭代cos结构，适用于altera。-Improved Iterative CORDIC algorithm cos structure, applicable to altera.
Platform: | Size: 8192 | Author: 金夕 | Hits:

[VHDL-FPGA-Verilog] cordic_generic

Description: 本人根据opencores.org上的cordic算法改写的可配置位宽的cordic算法，并且在原始的级联型的基础上编写的循环(iterative)型的cordic,可通过generic配置。带一个不可综合和可综合的testbench(for altera)。稍微改动可应用于xilinx fpga-a generic synthesizable cordic with 2 modes: cascade and iterative. based on opencores.org version, a synthesizable testbench please refer to www.opencores.org for documentation
Platform: | Size: 11264 | Author: Zhu | Hits:

[VHDL-FPGA-Verilog] cordiccos

Description: cordic算法的fpga的实现 采用altera芯片-cordic realization algorithm using fpga chip altera
Platform: | Size: 821248 | Author: liulei | Hits:

[VHDL-FPGA-Verilog] ram

Description: 基于altera ep2c8双口RAM -Altera ep2c8-based dual-port RAM
Platform: | Size: 884736 | Author: 秦学富 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: altera cordic ip core, 包含文档，完整设计，以及测试向量-altera coedic ip core, including the document, whole design, and the testbench.
Platform: | Size: 896000 | Author: panzhijian | Hits:

[VHDL-FPGA-Verilog] CORDIC_FPGA

Description: 摘要：本文在传统CORDIC算法的基础之上，通过增加迭代次数，对参数进行了优化筛选， 提高了运算精度，使设计出的软核能够在精度要求较高的场合中运行，如实时语音、图 像信号处理、滤波技术等。输出数据经过IEEE-754标准化处理，能够直接兼容大多数处 理器，扩展了其应用范围。最终在Altera公司NiosⅡ处理器中通过增加自定义指令的方 式完成了硬件实现。 关键字：CORDIC ,自定义指令, IEEE-754标准化处理。-Abstract: In this paper, based on the traditional CORDIC algorithm, by increasing the number of iterations, selection of parameters were optimized to improve the computing precision, the design of the soft-core to the occasion in the high precision in the running, such as real-time voice , image signal processing, filtering technology. IEEE-754 output data after standardization, can be directly compatible with most processors, expanded its scope of application. Altera, Nios Ⅱ ultimately by the processor the way to add custom instructions to complete the hardware. Keywords: CORDIC, custom instruction, IEEE-754 standard treatment.
Platform: | Size: 228352 | Author: daisywmc | Hits:

[VHDL-FPGA-Verilog] cordic

Description: cordic 算法的FPGA实现，在Altera公司CycloneIII系列EP3C240C8Q芯片上验证通过-the inplemention of cordic algorithm in FPGA
Platform: | Size: 1024 | Author: 黄宇 | Hits:

[Other] cordic

Description: Altera 的CORDIC IP核，Verilog HDL-Altera CORDIC IP core, Verilog HDL
Platform: | Size: 896000 | Author: 杨睿 | Hits:

[Software Engineering] The-Phase-Locked-Demodulation-

Description: 利用Altera公司推出的FPGA开发工具DSP Builder，对锁相解调算法中的主要部件：数控振荡器(NCO)、计算反正切的CORDIC模块和FIR低通滤波器进行了单独设计和仿真，最终完成了锁相解调系统的整体设计。-Designed and simulated major components of phase-locking Demodulation Algorithm independently, including: Number Controlled Oscillator(NCO)、CORDIC module used to compute the arc tangent and FIR low-pass filter by using Altera’s FPGA development tool DSP Builder. Completed the overall design of phase-locked demodulation system.
Platform: | Size: 2209792 | Author: 张强 | Hits:

[Program doc] ug_cordic

Description: cordic算法文档,适用于altera的FPGA-cordic docment
Platform: | Size: 118784 | Author: 朱明明 | Hits:

[VHDL-FPGA-Verilog] CORDIC_ATAN

Description: FPGA实现反正切功能，工程原件，包括测试文件，能够很好实现该功能(FPGA implements arctangent function, original engineering)
Platform: | Size: 6552576 | Author: TX_77846 | Hits:

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