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[Other] leon3-altera-ep2s60-ddr

Description: The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.-The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) developmen t. The IP cores are centered around a common on-c hip bus, and use a coherent method for simulation and syn thesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug
Platform: | Size: 103163 | Author: 岳昆 | Hits:

[VHDL-FPGA-Verilog] SRAM@DMA实验

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Platform: | Size: 33792 | Author: xf | Hits:

[VHDL-FPGA-Verilog] SPI接口音频Codec实验

Description: ALTERA NIOS处理器，VHDL语言在QUARTUS编译通过，然后有C语言在NIOS SHELL下驱动，实验音频解码-Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
Platform: | Size: 34816 | Author: xf | Hits:

[VHDL-FPGA-Verilog] VGA_example

Description: vga example for altera
Platform: | Size: 244736 | Author: 黃綜三 | Hits:

[Other] NiosSystemDesigned_C

Description: 本书以Altera公司开发的NIOS嵌入式处理器软核为例，介绍了嵌入式处理器的组成原理和开发应用。介绍NIOS系统设计和c程序编程与调试。-book to Altera NIOS development of the soft-core embedded processor as an example. on the embedded processor's architecture and application development. NIOS introduced c system design and programming and debugging.
Platform: | Size: 7921664 | Author: 阿康 | Hits:

[OpenGL program] yesadmin_com_20051126142245906

Description: ·以C#完成msn到jabber的tr. · 本游戏是采用斜45度. ·本源码是wis芯片完成mpeg. ·在VxWorks 编程过程中，. ·Raw Socket（原始套接字. ·基于OpenGL的ActiveX控件. ·Windows下的基于intel的i. ·Altera AHDL语言设计的PC. ·值得一看，对于网络管理. ·北京里工大学ASIC设计研. ·绝对经典的uc/os的程序，. ·1,本软件实现了围棋打谱,. ·日本著名的的嵌入式实时. ·ddos源代码,c语言。共同-C# to complete the msn to jabber tr. The game is the ramp 45 degrees. The FOSS wis chip is completed mpeg. In VxWorks programming process, . Raw Socket (original socket. OpenGL-based ActiveX. W indows under the intel-based Altera AHDL i. PC design. worth 1, for network management. Beijing University to work in ASIC design research. absolute classic uc/os procedures, . 1, the software Go to fight the spectrum. Prominent Japanese embedded real-time. ddos source code, c language. Common
Platform: | Size: 1908736 | Author: 大大 | Hits:

[Documents] C6X_Optimizing_summarization(chinese)

Description: 有关TI DSP c6000系列的C代码优化总结，对期数据打包、循环分解、内联函数的应用以及字节对齐等方面都有所介绍。-the TI DSP c6000 Series C code optimization summary view of data packing, recycling decomposition, Joint function within the application and byte alignment, and other aspects introduced.
Platform: | Size: 319488 | Author: 周国华 | Hits:

[Embeded-SCM Develop] hello_led_0

Description: 一个sd卡读写的源程序，这个程序是基于altera的嵌入式处理器nios的。不包含文件系统，代码简单明了，强烈推荐-A sd card reader of the source, this procedure is based on altera s Nios embedded processor. Does not contain a file system, the code is simple and clear, strongly recommend
Platform: | Size: 6144 | Author: 肖卫华 | Hits:

[Other] leon3-altera-ep2s60-ddr

Description: The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.-The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) developmen t. The IP cores are centered around a common on-c hip bus, and use a coherent method for simulation and syn thesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug
Platform: | Size: 103424 | Author: 岳昆 | Hits:

[Embeded-SCM Develop] NiosIIexample

Description: NIOSII的7个c语言源码，是7个例子，分别在niosII IDE环境下实现，不同的功能。是基于altera的标准c，目前资源较少。-NIOSII of 7 c language source code, is a seven examples, respectively realize niosII IDE environment, different functions. Is based on the altera standard c, currently fewer resources.
Platform: | Size: 15360 | Author: 朱峰 | Hits:

[VHDL-FPGA-Verilog] 2C35F672_FFT

Description: 在Altera芯片2C35F672平台上的FFT程序，采用DSPBuilder5.0，生成Verilog文件。开发环境：QuartusII5.0。-In the Altera chip 2C35F672 platform FFT procedures DSPBuilder5.0, generated Verilog file. Development Environment: QuartusII5.0.
Platform: | Size: 474112 | Author: lovenevol | Hits:

[VHDL-FPGA-Verilog] Maze_solver

Description: 走迷宫机器人C++源码。使用IR Sensor，P9000 电机，Altera 微处理器，L293D 控制芯片。 所有功能都有相应标注-Maze robot C++ Source. The use of IR Sensor, P9000 electrical, Altera microprocessor, L293D chip control. Have all the features of the corresponding marked
Platform: | Size: 3072 | Author: clark | Hits:

[ARM-PowerPC-ColdFire-MIPS] VGA

Description: 在Altera公司NIOS IDE开发中控制VGA显示，运行通过，可以直接移植，-Altera Corporation in the NIOS IDE development control VGA display, running through, can be directly transplanted
Platform: | Size: 1024 | Author: 罗生 | Hits:

[VHDL-FPGA-Verilog] xd_lcd_comp

Description: 一款240＊128的LCD模块在ALTERA　FPGA　NIOS中的应用，自己写的AVALON总线IP，包括所有源码，可轻松用于NIOS中，供大家参考-A 240* 128 LCD module in the ALTERA FPGA NIOS application, write your own AVALON Bus IP, including all source code can be easily used in NIOS for reference
Platform: | Size: 13312 | Author: 张敏 | Hits:

[VHDL-FPGA-Verilog] ofdm_cp_insertion_v71

Description: OFDM的fpga实现，用altera的器件！-OFDM realize the FPGA, using altera device!
Platform: | Size: 877568 | Author: 王海 | Hits:

[Other] make_interrupt_vector

Description: altera NIOS软核系统 中断矢量使用例子，基于C语言-altera NIOS soft-core system interrupt vector to use examples, based on the C language
Platform: | Size: 3072 | Author: 黄杰 | Hits:

[VHDL-FPGA-Verilog] DCT2IDCT2

Description: CT2 IDCT2 变换C代码。经调试成功，适用于altera,有结果。-CT2 IDCT2 transform C code. After successful testing for altera, bear fruit.
Platform: | Size: 1171456 | Author: 金夕 | Hits:

[Linux-Unix] altpciechdma.c

Description: altera pcie driver dma
Platform: | Size: 11264 | Author: long xu | Hits:

[VHDL-FPGA-Verilog] Altera+OpenCL

Description: Altera的OpenCL主要面向信号处理类应用的客户，是用C语言开发FPGA的利器，开放计算语言(OpenCL)联盟著名的公司有FPGA巨头Altera、两大显卡GPU巨头AMD、英伟达、CPU巨头Intel、软件和服务器巨头IBM以及全世界最大的公司Apple（苹果）等等。不过AMD和英伟达是用GPU实现的OpenCL并行运算，Altera是用FPGA实现并行运算。(Altera's OpenCL is mainly a client for signal processing applications, a tool for developing FPGA in the C language. The famous companies in the open computing language (OpenCL) alliance are FPGA giant Altera, two big card GPU tycoons AMD, Ying Weida, CPU giant Intel, software and server giants IBM, and the world's largest company (Apple) Wait. But AMD and Nvidia use GPU to implement OpenCL parallel computing, while Altera uses FPGA to implement parallel computing.)
Platform: | Size: 467968 | Author: CrazyICer | Hits:

[Other Embeded program] Loader FPGA Altera (C Source)

Description: Loader FPGA Altera (C Source).
Platform: | Size: 1730 | Author: vasil31 | Hits:
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