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Description: 使用Altera芯片实现对4个SAA7111A视频A/D芯片的采集控制,将图像数据存入同步FIFO-AL422B-use Altera chip to 4 SAA7111A Video A / D chip to control the collection, image data are stored in synchronous FIFO - AL422B
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Size: 1151 |
Author: 古韦剑 |
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Description: The example design provides a framework for rapid development of
video and image processing designs using the library of parameterizable
MegaCore® functions available in the Altera Video and Image Processing
Suite.
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Size: 1208938 |
Author: 普林斯 |
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Description: ALTERA的FPGA的IP核的源代码,为使用ALTERA的FPGA的相关设计提供参考.-Altera FPGA IP core of the source code for the use of Altera FPGA design to provide the relevant information.
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Size: 49152 |
Author: 汪旭 |
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Description: 使用Altera芯片实现对4个SAA7111A视频A/D芯片的采集控制,将图像数据存入同步FIFO-AL422B-use Altera chip to 4 SAA7111A Video A/D chip to control the collection, image data are stored in synchronous FIFO- AL422B
Platform: |
Size: 1024 |
Author: 古韦剑 |
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Description: The example design provides a framework for rapid development of
video and image processing designs using the library of parameterizable
MegaCore® functions available in the Altera Video and Image Processing
Suite.
Platform: |
Size: 1208320 |
Author: 普林斯 |
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Description: 内有一PCI 主 和PCI从,PCI TARGET 都是公开代码的,是工程文件,有仿真工程,使用说明。觉得好的就推荐一下。
本PCI_HOST目前支持:
1、 对目标PCI_T进行配置;
2、 对目标进行单周期读写;
3、 可以工作在33MHZ和66MHZ
4、 支持目标跟不上时插入最长10时钟的等待。
ALTERA的PCI竟然收费的!!!软件里面调试仿真了半天,终于调通了,到了下载就突然弹出窗口说包含了有限制的IP CORE,是限制使用的-There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of
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Size: 2712576 |
Author: |
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Description: Verilog的135个经典设计实例,直流电机控制,游戏机,三态总线,加法器,锁存器等-Verilog s 135 classic design example, DC motor control, video game consoles, three-state bus, adder, latches, etc.
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Size: 113664 |
Author: 何柳 |
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Description: Altera DE1 多媒体平台训练课程
视频教程-Altera DE1 training courses multimedia platform
Video tutorial
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Size: 7545856 |
Author: xiaoxu |
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Description: Splitter file to be used to split altera avalon st video stream into two avalon st streams.
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Size: 237568 |
Author: formjk |
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Description: VHDL code for UP2 board of Altera, that generate a video signal to VGA port.
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Size: 332800 |
Author: Lokous |
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Description: presentation a low cost video tracking algorithm implemented on an Altera DE2 board with Cyclone II processor. System uses a VGA controller and several SG-DMA s-presentation on a low cost video tracking algorithm implemented on an Altera DE2 board with Cyclone II processor. System uses a VGA controller and several SG-DMA s
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Size: 1514496 |
Author: stjohn |
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Description: This the artwork for a board that connects a video encoder chip to a Altera DE1 board (or any other) via a IDE cable-This is the artwork for a board that connects a video encoder chip to a Altera DE1 board (or any other) via a IDE cable
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Size: 15360 |
Author: ghost |
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Description: Altera公司原版设计手册,关于video and image processing ip-This document describes the Altera® Video and Image Processing Suite collection of
IP cores that ease the development of video and image processing designs. You can
use the following IP cores in a wide variety of image processing and display
applications.
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Size: 1402880 |
Author: Han Yunbo |
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Description: altera sdi ip core的使用例程-altera sdi ip core of the use of routine
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Size: 84992 |
Author: dido wang |
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Description: altera公司 图像处理方面的实例程序-the altera corporate image processing instance procedures
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Size: 1679360 |
Author: 余中意 |
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Description: altra nios II video system
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Size: 2598912 |
Author: rsa2013 |
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Description: 视频图像处理方法介绍altera公司相关文章-Video image processing method described in
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Size: 1646592 |
Author: 李群 |
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Description: <用FPGA实现高清视频去隔行功能>
本白皮书介绍各种去隔行技术,以及怎样使用Altera 的视频和图像处理IP 包来实现这些技术。采用视频设计方法,设计人员在实现不同的去隔行算法时,能够综合考虑各种硬件方案。-Using FPGA to achieve HD video de interlacing function
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Size: 1196032 |
Author: zblinux |
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Description: 介绍altera的video over ip的参考设计-The Altera ® Video Over IP Reference Design implements a system that
bridges between MPEG transport stream (TS) data and Ethernet-based
internet protocol (IP) networks.
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Size: 516096 |
Author: hife |
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Description: Altera® 高清晰度视频参考设计以隔行扫描或逐行扫描格式实现标准清晰度 (SD)、高
清晰度 (HD) 和 3 千兆位每秒 (Gbps) 视频流的高质量上变频、下变频和交叉变频 (UDX)
设计。-hd video design refrence files
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Size: 529408 |
Author: shen xiaoyu |
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