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[File Format] Advanced-Xilinx-FPGA

Description: Advanced Xilinx FPGA Design with ISE Objectives Describe Virtex™ -II advanced architectural features and how they can be used to improve performance • Create and integrate cores into your design flow using the CORE Generator™ System • Describe the different ISE options available and how they can be used to improve performance • Describe a flow for obtaining timing closure with Advance Timing Constraints • Use FloorPlanner to improve timing • Reduce implementation time with Incremental Design Techniques and Modular Design Techniques • Reduce debugging time with FPGA Editor • On-Chip Verification with ChipScope Pro-Advanced Xilinx FPGA Design with ISE Objectives Describe Virtex™ -II advanced architectural features and how they can be used to improve performance • Create and integrate cores into your design flow using the CORE Generator™ System • Describe the different ISE options available and how they can be used to improve performance • Describe a flow for obtaining timing closure with Advance Timing Constraints • Use FloorPlanner to improve timing • Reduce implementation time with Incremental Design Techniques and Modular Design Techniques • Reduce debugging time with FPGA Editor • On-Chip Verification with ChipScope Pro
Platform: | Size: 10615808 | Author: rakesh | Hits:

[VHDL-FPGA-Verilog] VHDLbaseddesignofmusicplayer

Description: 在EDA开发工具Quartus II 6.0平台上，采用VHDL语言层次化和模块化的设计方法，通过音符编码的设计思想，预先定制乐曲，实现动态显示乐曲演奏电路的设计，并在此基础上，基于同一原理，使此电路同时具备了简易电子琴的功能，使基于CPLD/FPGA芯片的乐曲播放数字电路得到了更好的优化，提高了设计的灵活性和可扩展性。- Based on the QuartusII-the EDA development tool, this design has adopted the method of classification and modularization of VHDL level. Through the concept of note coding, the design of dynamic music-displaying circuit is realized after the musical composition has been made in advance. On the basis of the above and the same principle, this electric circuit has the same function of a simple electronic organ. The design of CPLD/FPGA chip-based music-displaying digital circuit is greatly improved, and the flexibility and expansibility of the design are improved as well.
Platform: | Size: 97280 | Author: bianwei | Hits:

[VHDL-FPGA-Verilog] Timingbook

Description: Timing design for FPGA. Good document for advance learner of FPGA.
Platform: | Size: 376832 | Author: Frank Liu | Hits:

[VHDL-FPGA-Verilog] fpga

Description:
Platform: | Size: 17408 | Author: aa | Hits:

[VHDL-FPGA-Verilog] dds

Description: 通过查表法，用FPGA实现波形的输出。预先将数据存放在ROM中，依次读取数据并输出。-Look-up table method, the output waveform with FPGA implementation. Advance to data stored in ROM, in order to read data and output.
Platform: | Size: 2160640 | Author: 黄页中 | Hits:

[VHDL-FPGA-Verilog] advanced_fpga_qinghua

Description: FPGA设计高级进阶(清华大学电子工程系)-Advance FPGA design
Platform: | Size: 1051648 | Author: liyy | Hits:

[Software Engineering] Advance-HDL-Design-Training-On-Xilinx-FPGA

Description: dvance HDL Design Training On XilinxFPGA thanhmaikmt dao thanh mai
Platform: | Size: 2196480 | Author: DAO THANH MAI | Hits:

[Other] FPGA

Description: 设计一个电子琴，支持手动弹奏、自动演奏、弹奏回放等功能，具体要求如下： 可通过8个音符键产生8个频率（还可扩展），对应8个音符（中音1，2,3，4,5,6,7和高音1），这些频率输出经放大后驱动喇叭，发出声音。当按下手动弹奏键时，按下音符键后就选通相应的频率输出，若同时打开录音开关，可将所奏音乐记录下来，然后在关掉录音开关后，按下回放键可实现演奏音乐回放；按下自动演奏键时，存储器里事先编写好的音符信息被依次取出，去选通各个频率输出，实现自动奏乐。 -Can produce eight frequency (scalable) through eight note keys, corresponding to the eight notes (Alto 1, 2,3, 4,5,6,7 and treble 1), the output frequency by amplifying the speaker driver, sound. When pressing the manual plays the key, press the note keys after gating the corresponding frequency output, if at the same time the sound recording switch is turned on, will be playing the music recorded and after the tape off switch, press the playback button can realize music playback press automatic playing keys and memory in advance to write a good note information was successively extracted, to strobe output of each frequency, automatic playing music.
Platform: | Size: 673792 | Author: mary | Hits:

[VHDL-FPGA-Verilog] step_motor

Description: 2相混合式步进电机驱动程序，配套MC860H驱动器，共阴极接法 EN提前DIR至少5us，正常工作为高电平 DIR提前PUL下降沿5us确定其状态高或底，DIR 高：正转，底：反转 PUL脉冲信号，高电平不小于2.5us，低电平不小于2.5us(2 phase hybrid stepper motor driver, matching MC860H driver, common cathode connection method.EN advance DIR at least 5us, normal operation is high level, DIR ahead of PUL falls along 5us to determine its state of high or bottom, DIR high: positive turn, bottom: reverse PUL pulse signal, high level is not less than 2.5us, low level is not less than 2.5us)
Platform: | Size: 3173376 | Author: rabbiteee | Hits:

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