Description: 6级流水,verilog实现浮点数的加法,其中浮点数格式符合IEEE754标准-6 water, verilog realize the floating point adder, in which floating-point format in line with the IEEE754 standard Platform: |
Size: 2048 |
Author:兰兰 |
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Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算,结合vhdl和EPGA可编程技术,完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder. Platform: |
Size: 154624 |
Author:凌音 |
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Description: 这个fpadd程序应用verilog语言,实现的功能是简单的浮点加法器。初学的同学们可以一看。-This fpadd program applications verilog language to achieve the function is simple floating point adder. Beginner students can have a look. Platform: |
Size: 1024 |
Author:TD |
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Description: 该源码利用Verilog HDL语言成功实现了浮点数的加法运算,包括全部工程以及Verilog 源码,经验证,该程序成功实现了浮点数的加法。-The use of Verilog HDL source language of the successful implementation of floating-point addition operation, including all engineering and Verilog source code, proven, successful implementation of the program the floating point adder. Platform: |
Size: 12144640 |
Author:zhu yue |
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