Search - Vhdl rs

[Other resource] RS(32to28)encoderanddecoder

Description: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Platform: | Size: 77351 | Author: 王文 | Hits:

[Applications] RS encoder(Verilog)

Description: RS编码的源代码使用Verilog在Xinloinx平台-RS coding using the source code in Verilog Xinloinx platform
Platform: | Size: 5120 | Author: 王锋 | Hits:

[VHDL-FPGA-Verilog] RS232-for-vdhl

Description: RS232通讯VHDL源代码,MAXPLUS 2环境执行通过-RS232 communications VHDL source code, Segments 2 environment through implementation
Platform: | Size: 161792 | Author: lq | Hits:

[VHDL-FPGA-Verilog] RS_decoder

Description: rs编码vvhdl 希望能通过我不晓得具体对大家有用否希望懂rs编码的多多交流 -rs coding vvhdl I do not want to be able to know the specific useful whether you want to understand a lot of coding rs exchange
Platform: | Size: 15360 | Author: | Hits:

[VHDL-FPGA-Verilog] RS(32to28)encoderanddecoder

Description: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Platform: | Size: 76800 | Author: 王文 | Hits:

[Post-TeleCom sofeware systems] rs-code

Description: 基于PLD的RS码编译码器设计，用VHDL语言编写，编译通过，测试结果正确。-PLD-based encoding and decoding of RS code design, using VHDL language, the compiler is passed, the test results correctly.
Platform: | Size: 15360 | Author: li.j | Hits:

[VHDL-FPGA-Verilog] rs-5-3

Description: 学习使用FPGA做一些简单的编码器,RS(5,3)编码就是5个字符中有5-3=2两个校正字-Learning to use the FPGA to do a few simple encoders, RS (5,3) code is five characters in 5-3 = 2 has two correction words
Platform: | Size: 992256 | Author: rubyshirial | Hits:

[Communication-Mobile] RSencoder

Description: 关于rs码编码器的相关程序，利用硬件语言实现-Rs encoder code on the relevant procedures, take advantage of the hardware language
Platform: | Size: 5120 | Author: 庄镒鹏 | Hits:

[VHDL-FPGA-Verilog] RS(204_188)decoder

Description: <Verilog HDL 语言编程》 RS(204,188)译码器的设计-<Verilog HDL language programming RS (204,188) Decoder
Platform: | Size: 11264 | Author: 李映波 | Hits:

[VHDL-FPGA-Verilog] RS(31-19-6)

Description: reed-solomon译码器。共有7个文件，分别为译码器的7个模块。-reed-solomon decoder. A total of seven papers, respectively, the decoder module 7.
Platform: | Size: 9216 | Author: liwei | Hits:

[VHDL-FPGA-Verilog] RSdecoder

Description: cpld/fpga RS(204,188)译码器的verilog程序-cpld/fpga RS (204,188) decoder of the Verilog program
Platform: | Size: 13312 | Author: 陈臣 | Hits:

[VHDL-FPGA-Verilog] ps

Description: RS(204,188)译码器的设计异步FIFO设计伪随即序列应用设计 CORDIC数字计算机的设计 CIC的设计除法器的设计加罗华域的乘法器设计-RS (204188) decoder design of asynchronous FIFO design application design sequence was pseudo-CORDIC design of digital computer design CIC divider design Le Hua domain multiplier design
Platform: | Size: 48128 | Author: 苏晓东 | Hits:

[VHDL-FPGA-Verilog] rs-codec-8-16

Description: RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
Platform: | Size: 27648 | Author: 饶进平 | Hits:

[Other] RS_Verilog

Description: rs编解码的verilog实现源代码，从硬件实现rs的编解码-rs codec to achieve the verilog source code, from the hardware codec rs
Platform: | Size: 101376 | Author: 曹晶 | Hits:

[VHDL-FPGA-Verilog] RS

Description: reed selemon encoder vhdl code
Platform: | Size: 77824 | Author: mohamed saad | Hits:

[3G develop] verilogHDL

Description: RS（31，15）译码关键步骤的veilog HDL算法实现，包括关键方程求解，错误位置估计，错误值计算等-RS (31,15) decoding a key step in the algorithm veilog HDL, including key equations, position estimation error, error value, such as
Platform: | Size: 12288 | Author: 冯小刚 | Hits:

[VHDL-FPGA-Verilog] 232

Description: 实现PS/2接口与RS-232接口的数据传输，可以通过RS-232自动传送到主机的串口调试终端上并在数据接收区显示接收到的字符。-The realization of PS/2 port RS-232 interface with data transfer, RS-232 can be automatically sent to the host serial debug terminal and reception area in the data display received characters.
Platform: | Size: 15360 | Author: 包宰 | Hits:

[Other] RS(204.188)design

Description: RS(204,188)译码器说明原文件： rs_decoder.v（顶层文件）, SyndromeCalc.v（计算伴随式）, BM_KES.v（BM求解关键方程）, Forney.v（Forney算法求误差样值）, CheinSearch.v（搜索错误位置）,ff_mul.v（有限域乘法）。 ROM及初始化文件： rom_inv.v（求逆运算）, rom_power.v（求幂运算）； rom_inv.mif（ROM初始化文件）, rom_power.mif（ROM初始化文件）。仿真波形： rs_decoder.vwf。-RS (204,188) decoder that the original document: rs_decoder.v (top-level document), SyndromeCalc.v (calculated Syndrome), BM_KES.v (BM key equation solving), Forney.v (Forney algorithm for error-like value), CheinSearch.v (search the wrong location), ff_mul.v (finite field multiplication). ROM and the initialization file: rom_inv.v (inverse operation), rom_power.v (for power calculations) rom_inv.mif (ROM initialization file), rom_power.mif (ROM initialization files). Simulation waveforms: rs_decoder.vwf.
Platform: | Size: 14336 | Author: 川天古木 | Hits:

[VHDL-FPGA-Verilog] RS

Description: RS编码器的VHDL源程序,程序有点大，不过能用。-RS encoder VHDL source code, program a little big, but can be used.
Platform: | Size: 897024 | Author: lcz | Hits:

[VHDL-FPGA-Verilog] RS

Description: 基于FPGA的RS编码，包括RS码的编码原理，RS电路的设计与实现-FPGA-based RS code, including the RS, the coding principle, RS Circuit Design and Implementation
Platform: | Size: 1132544 | Author: 陈凯 | Hits:

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[Other resource] RS(32to28)encoderanddecoder

[Applications] RS encoder(Verilog)

[VHDL-FPGA-Verilog] RS232-for-vdhl

[VHDL-FPGA-Verilog] RS_decoder

[VHDL-FPGA-Verilog] RS(32to28)encoderanddecoder

[Post-TeleCom sofeware systems] rs-code

[VHDL-FPGA-Verilog] rs-5-3

[Communication-Mobile] RSencoder

[VHDL-FPGA-Verilog] RS(204_188)decoder

[VHDL-FPGA-Verilog] RS(31-19-6)

[VHDL-FPGA-Verilog] RSdecoder

[VHDL-FPGA-Verilog] ps

[VHDL-FPGA-Verilog] rs-codec-8-16

[Other] RS_Verilog

[VHDL-FPGA-Verilog] RS

[3G develop] verilogHDL

[VHDL-FPGA-Verilog] 232

[Other] RS(204.188)design

[VHDL-FPGA-Verilog] RS

[VHDL-FPGA-Verilog] RS

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