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[VHDL-FPGA-Verilog] add

Description: 介绍了carry_chain_adder，carry_skip_adder,ipple_carry_adder三种常用的加法器，采用verilogHDL语言，利用modelsim软件仿真验证，压缩包中包含有流程图-Introduced carry_chain_adder, carry_skip_adder, ipple_carry_adder three commonly used adder, using verilogHDL language, the use of ModelSim simulation software, compressed packet contains flowchart
Platform: | Size: 372736 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] CORDIC_DDS_16bit

Description: dds频率生成文件，看看有没有人喜欢认真阅读您的文件包然后写出其具-dds frequency generated files, see if there is no one really wants to read your document carefully and then write its packet with
Platform: | Size: 1357824 | Author: zhangxi | Hits:

[mpeg mp3] mp3decoder

Description: mp3 解码的verilog代码，通过仿真综合及验证，能够播放所有的.mp3文件。压缩包包括所有的verilog源码以及详细的文档。-mp3 decoding Verilog code, the adoption of an integrated simulation and verification, can all play. mp3 file. Compressed packet including all the Verilog source code and detailed documentation.
Platform: | Size: 169984 | Author: 刘名 | Hits:

[VHDL-FPGA-Verilog] traffic

Description: verilog编写的一个交通灯程序，利用状态机实现。压缩包内有说明文档，源代码及时序截图-verilog prepared a program of traffic lights, the use of state machine to achieve. Compressed packet, there are documentation, source code and timing Screenshots
Platform: | Size: 497664 | Author: 尹力超 | Hits:

[VHDL-FPGA-Verilog] smii_latest.tar

Description: SMII接口的mac控制器，通过测试。使用verilog语言！-The Serial Media Independent Interface, SMMI, is a low pin count version of the MII normally used between ethernet MAC and PHY. The Serial Media Independent Interface (SMII) is designed to satisfy the following requirements: Convey complete MII information between a 10/100 PHY and MAC with two pins per port allow multi port MAC/PHY communications with one system clock Operate in both half and full duplex per packet switching between 10 Mbit and 100 Mbit data rates allow direct MAC to MAC communication
Platform: | Size: 1035264 | Author: weixin | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 题目在压缩包中,如：设计4 位超前进位加法器。并给出测试模块和测试分析结 果。 -topic in the packet
Platform: | Size: 458752 | Author: 宝路 | Hits:

[VHDL-FPGA-Verilog] System_Demons

Description: 0.最简单的SystemC程序：hello, world. 1.用SystemC实现D触发器的例子，同时也演示了如何生成VCD波形文件。 2.用SystemC实现同步FIFO的例子。这个FIFO是从同文件夹的fifo.v（verilog代码）翻译过来的。 3.如何在SystemC中实现延时（类似verilog中的#time）的例子。 4.SystemC文档《User Guide》中的例子。注意和文挡中稍有不同的是修改了packet.h文件，重载了=和<<操作符。这其实也演示了在sc_signal中如何使用用户自定义的struct。 5.构造函数带参数的例子。 6.轮转仲裁的例子。 7.使用类摸板的例子。 8.如何在模块中包含子模块。 9.SystemC的Transaction级验证示例。 10.如何trace一个数组 11.SystemC中使用测试向量文件输入的例子。 12.SystemC采用UDP/TCP通信的例子。 13.Cadence的ncsc的例子。 -0 most simple SystemC program: hello, world. A D flip-flop using SystemC example also demonstrates how to generate VCD waveform files. Synchronous FIFO example using SystemC. FIFO is from the same folder fifo.v (Verilog code) translated. Delay (similar to verilog# time). In SystemC examples. 4.SystemC document the "User Guide" in the example. Note the slightly different cultural block is modified the packet.h file, reload = << operator. In fact, this also demonstrates how to use user-defined struct in sc_signal. Constructor with parameters example. (6) examples of web arbitration. 7. The class Moban examples. 8 module contains a sub-module. 9.SystemC of Transaction-Level Verification example. 10 How to trace an array 11.SystemC use the example of the test vector file input. 12.SystemC using the example of the UDP/TCP communication. Examples of 13.Cadence the ncsc.
Platform: | Size: 532480 | Author: sdd | Hits:

[VHDL-FPGA-Verilog] ingress

Description: Verilog 实现1588协议的报文解析功能-Verilog 1588 packet analysis function
Platform: | Size: 31744 | Author: Arnold | Hits:

[Internet-Network] ETH_GEN_CHK

Description: Ethernet packet generator and check (verilog),for Ethernet design purpose!
Platform: | Size: 3072 | Author: min | Hits:

[VHDL-FPGA-Verilog] random_check

Description: 随机码流中的报文捕捉器，Verilog编写，本报文捕捉器用于记录报文中数字信号“1”的个数。当报文捕捉器检测到随机码流中出现“1101”的序列后，确认为报头，并开始对后续正式报文中的“1”进行计数，针对AX516系统开发板(A message trap in a random stream, written by Verilog, is used to record the number of "1" in a message. When the packet capture device detects the sequence of "1101" appearing in the random code stream, it is recognized as the header and begins to count the "1" in the subsequent official message, aiming at the development board of the AX516 system.)
Platform: | Size: 975872 | Author: wanwan000 | Hits:

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