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[SourceCode] verilog交通灯

Description: 文件实现了比较复杂的交通灯设计，在Quartus II中编译通过，波形正确
Platform: | Size: 524112 | Author: 15124510677@163.com | Hits:

[VHDL-FPGA-Verilog] key_scan1

Description: 用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功-achieved using Verilog 4 x 4 keyboard procedures, the Quartus II compiler on the adoption and successful
Platform: | Size: 594944 | Author: 大圣 | Hits:

[Books] Quartus-guide

Description: quartus的教程，是初学者使用FPGA的好老师，介绍了quartus的使用方法，并且有例子-quartus curricula, the use of FPGA beginners is a good teacher. quartus introduced the use, and is an example
Platform: | Size: 1183744 | Author: mh | Hits:

[Embeded-SCM Develop] quartusGuide

Description: 设计输入 ! 多种设计输入方法 – Quartus II • 原理图式图形设计输入 • 文本编辑 – AHDL, VHDL, Verilog • 内存编辑 – Hex, Mif – 第三方工具 • EDIF • HDL • VQM – 或采用一些别的方法去优化和提高输入的灵活性: • 混合设计格式 • 利用LPM和宏功能模块来加速设计输入-design input! Design a variety of input methods-Quartus
Platform: | Size: 844800 | Author: fgghh | Hits:

[Crack Hack] des

Description: 用VERILOG语言实现的数据加密标准代码,在QUARTUS5.1上仿真过-Using Verilog language code of the Data Encryption Standard, in the simulation had QUARTUS5.1
Platform: | Size: 1436672 | Author: zhang feng | Hits:

[VHDL-FPGA-Verilog] altera_ram

Description: 本程序对如何使用altera系列芯片片上ram进行实例演示，采用Verilog HDL语言编写，并使用modelsim与quartus联合进行功能仿真。本原码是红色逻辑开发板的试验程序，值得一看。-This procedure of how to use the altera series chip-chip ram for example demonstration, using Verilog HDL language, and using ModelSim and Quartus functional simulation carried out jointly. Primitive code is red logic development board of the pilot program, worth a visit.
Platform: | Size: 180224 | Author: panyouyu | Hits:

[VHDL-FPGA-Verilog] eeprom

Description: eeprom的Verilog HDL源代码，含eeprom的读写！Quartus II5.0平台测试通过！-EEPROM of the Verilog HDL source code, including reading and writing EEPROM! Quartus II5.0 platform test!
Platform: | Size: 521216 | Author: | Hits:

[VHDL-FPGA-Verilog] FPGA-SD-COMMUNICATION

Description: 基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信 所用语言位verilog HDL-QUARTUSII software implementation based on FPGA (ATERA CYCLONE II series) with SD Card SD mode digital communication language verilog HDL
Platform: | Size: 5064704 | Author: chenbinjie | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: Quartus II工程压缩文件，是一个典型的基于FPGA的秒表工程项目，有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language.
Platform: | Size: 464896 | Author: kg21kg | Hits:

[VHDL-FPGA-Verilog] pwm

Description: verilog实现PWM 开发环境 QUARTUS II7.0-verilog to achieve PWM development environment QUARTUS II7.0
Platform: | Size: 54272 | Author: exun | Hits:

[VHDL-FPGA-Verilog] report-hex-keypad-debouncer

Description: Quartus Verilog HDL, complete document, having schematics, flowcharts, and Verilog codes for various modules for implementing a hex-keypad, including the important code of DEBOUNCER
Platform: | Size: 797696 | Author: ak | Hits:

[VHDL-FPGA-Verilog] quartus-work

Description: 基于FPGA的VERILOG的分频器的设计，10分频设计的源代码和设计思路-Based od FPGA
Platform: | Size: 2048 | Author: 熊淑芬 | Hits:

[Other] lcd2tft

Description: convert lcd 4 bits to tft 16 bits.Writen verilog,Altera Quartus.
Platform: | Size: 816128 | Author: ulsonic | Hits:

[VHDL-FPGA-Verilog] horse_light4

Description: 六种花样的流水灯，从左至右，从右至左，中间向两边，两边向中间，跳格闪烁等。verilog语言编写； 并且扩展容易； 有两个状态机构成实现。quartus 9.0和7.1仿真通过。无错误，无警告。-Six kinds of patterns of flowing water lights, from left to right, from right to left, in the middle to both sides, both sides toward the middle, jumping grid flicker. And expansion easy there are two state agencies into a realization. quartus 9.0 and 7.1 by simulation. Error-free, no warning.
Platform: | Size: 69632 | Author: tangjieling | Hits:

[Software Engineering] Stepper_controller_MAx

Description: stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog quartus and modelsim implementation is also awailable -stepper motor controller vhdl and verilog code is given with explainintion testbench in verilog quartus and modelsim implementation is also awailable
Platform: | Size: 76800 | Author: pravin | Hits:

[Other] ddr-sdram-verilog-resource

Description: 描述了ddr_sram的源代码,包括SDRAM的引脚功能介绍和Verilog在modulesim及quartus ii的实现-description the resource code of ddr_sram
Platform: | Size: 896000 | Author: wangyuzhuo | Hits:

[VHDL-FPGA-Verilog] fifo-verilog

Description: 自己设计的一种FIFO寄存器，用verilog 编写，QUARTUS II下验证-Own design of a FIFO register, with verilog preparation, QUARTUS II certification under
Platform: | Size: 5120 | Author: wait | Hits:

[VHDL-FPGA-Verilog] mips

Description: MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
Platform: | Size: 5120 | Author: 王龙 | Hits:

[VHDL-FPGA-Verilog] rs232-Quartus

Description: 利用verilog語法,來達成串口rs232的功能-Using verilog syntax, to achieve the functions of serial rs232
Platform: | Size: 480256 | Author: 張三 | Hits:

[VHDL-FPGA-Verilog] verilog-vga

Description: Verilgo编写的VGA显示接口示例程序, 在显示器上显示矩形彩条, 包含Quartus II 8.1工程文件及VGA的相当资料(PDF及WORD文档)-Verilgo prepared VGA display interface sample program, the color of the rectangle on the display, including the Quartus II 8.1 project file and VGA considerable data (PDF and WORD document)
Platform: | Size: 1771520 | Author: Joseph | Hits:
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