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[VHDL-FPGA-VerilogDctInH264

Description: 这个是华清远见 高级班 培训的 实验 代码(vhdl)-This is an advanced course training vision Huaqing experimental code (vhdl)
Platform: | Size: 2048 | Author: 陈晓 | Hits:

[Software Engineeringxingxingyu1340

Description: This paper presents the results of the Finnish national "Technology Vision of the Future Distribution Network" project. The aim of the project was to create a technology vision of future distribution networks. Because the life span of networks is very long, a long term vision is very important for guiding network investments and technology development.
Platform: | Size: 345088 | Author: 何平 | Hits:

[Special Effectsthe_stud_of_high-speed_image_processing_for_machin

Description: 机器视觉中高速图象处理方法的研究以及FPGA的实现-Machine vision in the high-speed image processing methods, as well as the realization of FPGA
Platform: | Size: 2932736 | Author: 许小姐 | Hits:

[VHDL-FPGA-Verilogstereo_vision

Description: Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical and the sub-circuits can be used as smaller benchmarks.
Platform: | Size: 420864 | Author: junsung | Hits:

[VHDL-FPGA-Verilogrobertvision

Description: 基于FPGA的嵌入式机器人视觉识别系统模块源代码,也包括了所有硬件设计资料,是VERILOG格式-Embedded FPGA-based Robot Vision Recognition System module source code, including all hardware design information
Platform: | Size: 977920 | Author: lilei | Hits:

[VHDL-FPGA-VerilogFPGA2

Description: 华清远见FPGA 第2讲、FPGA设计入门2 视频-Huaqing vision FPGA Part 2, FPGA design entry-2 video
Platform: | Size: 5810176 | Author: 林方 | Hits:

[VHDL-FPGA-VerilogFPGA2-4

Description: 华清远见视频,FPGA入门视频第二讲第4部分-Huaqing vision video, FPGA Introduction Video Part 4 of the second stress
Platform: | Size: 9293824 | Author: 林方 | Hits:

[Otherfpga

Description: 华清远见的fpga应用开发与典型实例,第二章内容-Huaqing vision fpga application development and a typical example, the second chapter
Platform: | Size: 1759232 | Author: 李喆 | Hits:

[VHDL-FPGA-Verilog6

Description: 4位数码扫描显示电路,我们控制一个七段LED需要8个输出端口;如果要输出四位十进制数,就需要32的输出端口,这将占用大量的端口资源。采用串行扫描显示,我们只需要8+4共12个端口即可。其原理是:用一个四位的输出端控制,某一时刻只选中其中的一个LED(输出为‘1’表示选中),八位的输出端将该LED所需要显示的值输出;然后四位的输出端值改变,选中下一个LED。这样依次类推。如果选择的频率很快,达到50Hz以上,由于人眼的视觉暂留效应,看起来就像4个LED同时显示。 设计一个程序,输入四个一位十进制数,用4个LED显示出来。CLK采用频率可调信号发生器,逐渐改变频率,观察扫描频率的改变对输出效果的影响。 输入:连续脉冲,逻辑开关;输出:七段LED。 -4 digital scanning display circuit, we need to control a seven-segment LED output port 8 If you want to output four decimal numbers, you need the output port 32, which will take up a lot of ports. Serial scans showed, we need only 8 of 12 ports can be+4. The principle is: the output of four with a control, a time to select only one LED (output 1 is selected), 8 output of the LED by the need to show the value of the output then The output value of the four changes, select the next LED. This and so on. If you select the frequency rapidly, reaching more than 50Hz, as the human eye s persistence of vision effect, looks like a 4 LED display simultaneously. Design a program, enter a decimal number four, with four LED display. CLK signal generator with adjustable frequency, gradually changing the frequency of observed changes in scan frequency effect on the output. Input: Continuous pulse, logic switches output: seven-segment LED.
Platform: | Size: 4096 | Author: 李小勇 | Hits:

[Embeded-SCM Developnainaolei

Description: Code, there are very complete notes and explanations Very suitable for the study using computer vision, Achieve serial data acquisition.
Platform: | Size: 5120 | Author: beifentuiben | Hits:

[VHDL-FPGA-VerilogMVA15_Japan_Harris_FPGA_Vivado_source

Description: Harris 角点检测 FPGA实现 Tak Lon Chao, Kin Hong Wong, "An efficient FPGA implementation of the Harris Corner feature detector" Code:in VHDL and Verliog running on Zedboard(Tak Lon Chao, Kin Hong Wong, "An efficient FPGA implementation of the Harris Corner feature detector", The 14th IAPR Conference on Machine Vision Applications (MVA 2015), MIRAIKAN: National Museum of Emerging Science and Innovation in Tokyo, Japan, 18-22 May 2015 video1 video2 Code:in VHDL and Verliog running on Zedboard)
Platform: | Size: 19456 | Author: sudohello | Hits:

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