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[Other resource] VHDL语言100例详解

Description: VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.
Platform: | Size: 6634118 | Author: 穆群生 | Hits:

[VHDL-FPGA-Verilog] VHDL语言100例详解

Description: VHDL语言100例详解。详细讲解了用VHDL语言进行数字电路和数字系统设计的知识。用100个实例，不仅进行基础的门电路设计，而且还有较为复杂的数字系统设计。这些实例可以直接被调用。-VHDL Elaborates on 100 cases. Detailed account of VHDL for digital circuits and digital systems design knowledge. With 100 examples, not only for infrastructure gate design, but also more complex digital system design. These examples can be called.
Platform: | Size: 6633472 | Author: 穆群生 | Hits:

[VHDL-FPGA-Verilog] 分频器VHDL描述

Description: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。-in digital circuits, the need for regular high frequency clock operating frequency for hours, a lower frequency of the clock signal. We know that the hardware circuit design clock signal is very important.
Platform: | Size: 5120 | Author: 王力 | Hits:

[Other] VHDL

Description: 东南大学电工电子实验中心徐莹隽老师的VHDL数字系统设计，对于VHDL的初学者非常适合。-Southeast University, Electrical and Electronic Experiment Center Jun Xu Ying teachers VHDL digital system design, the VHDL is well suited for beginners.
Platform: | Size: 1509376 | Author: 杨春山 | Hits:

[Other] MDCT

Description: MPEG MDCT的一些文章 A design on the vector-processor of MDCT-IMDCT algorithm for digital audio；A fast algorithm of integer MDCT for lossless audio coding-MPEG MDCT articles A design on the vector-processor of MDCT-IMDCT algorithm for digital audio A fast algorithm of integer MDCT for lossless audio coding
Platform: | Size: 5156864 | Author: dingying | Hits:

[Embeded-SCM Develop] mydds

Description: Direct Digital Synthesis (DDS),最好用的可步进的数字频率发生器的方法，此代码本人亲自编写，用于当年电子设计大赛。注意其中有个模块用于与单片机通信，可以使用、下载到芯片中，仅供学习使用！-Direct Digital Synthesis (DDS), the best use of the digital frequency generator step method, the code I am personally prepared for electronic design contest that year. Attention which has modules for single-chip communication, you can use to download to the chip, only learning to use!
Platform: | Size: 8192 | Author: cjs | Hits:

[VHDL-FPGA-Verilog] train

Description: 用 VHDL语言实现闹钟功能，可用于数字钟设计的单元电路，显示电路程序。-Using VHDL language realize alarm function, can be used for the design of digital clock circuit, display circuit procedures.
Platform: | Size: 1024 | Author: 李林 | Hits:

[VHDL-FPGA-Verilog] alu181

Description: alu运算器vhdl代码，介绍了16中运算方法，可用于cpu的设计中-alu calculator VHDL code, introduction of 16 in computing methods, can be used for the design of cpu
Platform: | Size: 1024 | Author: 赵心 | Hits:

[VHDL-FPGA-Verilog] LC3-VHDL-another

Description: 另一套LC3 CPU VHDL源码及设计文档，对LC3进行了一些取舍和改造，比如NZP改为NZC，更贴近现实CPU硬件架构。按照ASM进行VHDL编码，更适合数字设计初学者学习。-Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design more suitable for beginners to learn.
Platform: | Size: 808960 | Author: guo | Hits:

[VHDL-FPGA-Verilog] Digital-Design-and-Computer-Architecture-VHDL

Description: 《数字设计和计算机体系结构》一书MIPS VHDL源码。
Platform: | Size: 4096 | Author: guo | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码-Digital System Design full adder, 10 hexadecimal counter ,2-4 decoder, Moore state machine ,2-1 MUX source code
Platform: | Size: 901120 | Author: 李帆 | Hits:

[VHDL-FPGA-Verilog] multifunction_digital_clock_based_on_fpga

Description: 基于FPGA的多功能数字钟的设计与实现 内附有详尽的Verilog HDL源码，其功能主要有：时间设置，时间显示，跑表，分频，日期设置，日期显示等-FPGA-based multi-functional Digital Clock Design and Implementation of typhoons and rainstorms are detailed Verilog HDL source code, its functions include: time settings, time display, stopwatch, frequency, date setting, date display
Platform: | Size: 3293184 | Author: | Hits:

[VHDL-FPGA-Verilog] adder_32

Description: 超前进位加法器是通常数字设计所必备的，本程序为32位超前进位加法器-CLA is usually necessary for digital design, the procedure for 32-bit CLA
Platform: | Size: 1024 | Author: zhaohongliang | Hits:

[Other] VerilogHDL

Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
Platform: | Size: 79872 | Author: sundan | Hits:

[VHDL-FPGA-Verilog] book

Description: Verilog HDL与VHDL都是数字系统设计的硬件描述语言，VerilogHDL适合算法级，rtl，逻辑级，门级，而VHDL适合特大型的系统级设计。针对这些特点这两本书深入浅出的介绍了这两种语言。-Verilog HDL and VHDL design of digital systems is the hardware description language, VerilogHDL suitable algorithm level, rtl, logic level, gate-level, and large VHDL for system-level design. In response to these characteristics of these two books in simple terms to introduce the two languages.
Platform: | Size: 15562752 | Author: 龙英 | Hits:

[VHDL-FPGA-Verilog] shuzitongxinxitongjianmo04

Description: 基于CPLD_FPGA的数字通信系统建模与设计，本学习资料共分为4个部分，此为第四部分，供对数字通信系统建模和设计有兴趣的朋友学习参考。-CPLD_FPGA based on the digital communication system modeling and design, the learning materials is divided into four parts, this is the fourth part of the digital communication system for modeling and design of friends interested in learning reference.
Platform: | Size: 1661952 | Author: wangjianan | Hits:

[Other] CPLDandVHDL

Description: Digital Design with CPLD Applications & VHDL - This book is aimed on beginner level and for proffesionals. It has more than 800 pages, where gived not only VHDL, but theory of all digital devices-Digital Design with CPLD Applications & VHDL- This book is aimed on beginner level and for proffesionals. It has more than 800 pages, where gived not only VHDL, but theory of all digital devices
Platform: | Size: 7409664 | Author: vahis | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 数字秒表的VHDL代码。当设计文件加载到目标器件后，设计的数字秒表从00-00-00开始计秒。，直到按下停止按键（按键开关S2）。数码管停止计秒。按下开始按键（按键开关S1），数码管继续进行计秒。按下复位按键（核心板上复位键）秒表从00-00-00重新开始计秒。-The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stopwatch count the seconds from the 00-00-00. Until you press stop key (key switch S2). Nixie tube stop count seconds. Press the start button (key switch S1), the digital control continue to count seconds. Press the reset button (core panel reset button) to restart the stopwatch count seconds from the 00-00-00.
Platform: | Size: 1024 | Author: 王唐小菲 | Hits:

[Other] VHDL-hard-describe-language

Description: 《VHDL硬件描述语言》 本书全面地介绍了VHDL硬件描述语言的基础知识和利用VHDL语言进行数字电路系统设计的方法。-" VHDL hardware description language," This book introduces the basic VHDL hardware description language knowledge and use of VHDL for digital circuit design approach.
Platform: | Size: 7918592 | Author: ding | Hits:

[VHDL-FPGA-Verilog] VHDL-based-digital-clock-programming

Description: 基于VHDL的数字时钟设计，可以调时间，并且可以设置四个闹钟时间，中和很多VHDL的基本程序，对初学者很有用-VHDL-based digital clock design, you can adjust the time, and you can set four alarm time, and in a lot of VHDL basic procedures, useful for beginners
Platform: | Size: 10240 | Author: 卢 | Hits:
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