Search - VHDL decoder

[VHDL-FPGA-Verilog] hdb3 decoder

Description: 我上期做的VHDL设计方案，用于在FPGA或CPLD中实现HDB3的编码-I do view on the VHDL design options for the CPLD or FPGA to achieve HDB3 code
Platform: | Size: 119808 | Author: 王薇 | Hits:

[SCM] VHDL范例

Description: 最高优先级编码器 8位相等比较器三人表决器（三种不同的描述方式）加法器描述 8位总线收发器：74245 （注2）地址译码（for m68008）多路选择器（使用select语句） LED七段译码多路选择器（使用if－else语句）双2－4译码器：74139 多路选择器（使用when－else语句）二进制到BCD码转换多路选择器（使用case语句）二进制到格雷码转换双向总线（注2）汉明纠错吗译码器三态总线（注2）汉明纠错吗编码器解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 43008 | Author: kerty | Hits:

[VHDL-FPGA-Verilog] decoder(vhdl)

Description: 这是用VHDL编写的译码程序,程序简单易懂-VHDL prepared decoding procedures that are simple to understand
Platform: | Size: 107520 | Author: 黄鹏飞 | Hits:

[VHDL-FPGA-Verilog] 8b10b_Decoder

Description: 应用VHDL设计的8b10b解码器源文件，实现高速的串行数据传输。-application VHDL design 8b10b decoder source, the realization of high-speed serial data transmission.
Platform: | Size: 18432 | Author: | Hits:

[Other] project_asic.tar

Description: MP3解码的ASIC全部过程，含c和vhdl-MP3 decoder ASIC whole process, with c and vhdl
Platform: | Size: 1262592 | Author: 丝绒 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: VHDL程序集锦，很多有用程序，英文版其中有汉明码编译码，优先译码等等。-VHDL Collection procedures, many useful procedures, the English version of them hamming code encoding and decoding, the priority decoder and so on.
Platform: | Size: 168960 | Author: 萍果 | Hits:

[VHDL-FPGA-Verilog] JM86

Description: 3－8 VHDL 译码器请-3-8 VHDL decoder, please
Platform: | Size: 10106880 | Author: 庞志勇 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 数字系统设计中的全加器、10进制计数器、2-4译码器、摩尔状态机、2-1路选择器的源代码-Digital System Design full adder, 10 hexadecimal counter ,2-4 decoder, Moore state machine ,2-1 MUX source code
Platform: | Size: 901120 | Author: 李帆 | Hits:

[VHDL-FPGA-Verilog] RS(204_188)decoder

Description: <Verilog HDL 语言编程》 RS(204,188)译码器的设计-<Verilog HDL language programming RS (204,188) Decoder
Platform: | Size: 11264 | Author: 李映波 | Hits:

[VHDL-FPGA-Verilog] dec.vhd

Description: vhdl code for a 16 bit decoder design
Platform: | Size: 2048 | Author: siluyuan | Hits:

[VHDL-FPGA-Verilog] BCHencodeanddecode

Description: bch 编码和译码，用硬件语言vhdl实现-bch edcode and decoder
Platform: | Size: 175104 | Author: 唐娇 | Hits:

[VHDL-FPGA-Verilog] Seven-Segment-Decoder

Description: 用VHDL语言在FPGA上实现将十进制bcd码转换成七段led显示码-FPGA using VHDL language to achieve will be converted to decimal bcd yards led seven segment display code
Platform: | Size: 1024 | Author: 吴金通 | Hits:

[DSP program] h264.tar

Description: h264解码器，包含详细的结构介绍，详细介绍了使用配置和端口说明-h264 decoder, the structure contains a detailed introduction, detailed description of the use of configuration and port
Platform: | Size: 806912 | Author: nickye | Hits:

[mpeg mp3] H.264

Description: 关于h.264视频解码器完全源码（verilog）-With regard to h.264 video decoder full source code (verilog)
Platform: | Size: 836608 | Author: 李风志 | Hits:

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[VHDL-FPGA-Verilog] hdb3 decoder

[SCM] VHDL范例

[VHDL-FPGA-Verilog] decoder(vhdl)

[VHDL-FPGA-Verilog] 8b10b_Decoder

[Other] project_asic.tar

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] JM86

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] RS(204_188)decoder

[VHDL-FPGA-Verilog] dec.vhd

[VHDL-FPGA-Verilog] BCHencodeanddecode

[VHDL-FPGA-Verilog] Seven-Segment-Decoder

[DSP program] h264.tar

[mpeg mp3] H.264

[VHDL-FPGA-Verilog] decoder

[Embeded-SCM Develop] decoder

[ELanguage] 16b20b_Decoder

[VHDL-FPGA-Verilog] 2-Decimal-BCD-Decoder

[2D Graphic] H.264Decoder

[source in ebook] decoder

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