Search - VHDL algorithms code

[Other] CORDIC-algorithms

Description: cordic算法的详细介绍，方便大家使用和研究-cordic detailed description of the algorithm, to facilitate the use and research
Platform: | Size: 122880 | Author: mh | Hits:

Description: 这是一个二维 8*8块的离散余弦变换(DCT)以及反变换(IDCT)算法,采用VHDL实现-This is a two-dimensional 8* 8 discrete cosine transform (DCT) and inverse transform (IDCT) algorithms using VHDL realize
Platform: | Size: 10240 | Author: liujl | Hits:

[VHDL-FPGA-Verilog] DA_FIR

Description: 基于分布式算法的FPGA实现的FIR滤波器源码，VHDL语言编写的，下载工程文件后可直接在QuartusII7.0上运行。-Based on Distributed algorithms realize the FIR filter FPGA source code, VHDL language, download the project file can be run directly in QuartusII7.0.
Platform: | Size: 531456 | Author: CH | Hits:

[VHDL-FPGA-Verilog] huffman

Description: 用于FPGA的huffman算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 10240 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] quant

Description: 用于FPGA的量化算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 14336 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] rle

Description: 用于FPGA的变长编码算法的HDL编码，包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Variable-length encoding for FPGA HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 4096 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] zigzag_decode

Description: 用于FPGA的反Z变换算法的Verilog代码。可用于JPEG及MPEG压缩算法。-FPGA for the anti-Z transform algorithm of Verilog code. Can be used in JPEG and MPEG compression algorithms.
Platform: | Size: 3072 | Author: caesar | Hits:

[VHDL-FPGA-Verilog] edge

Description: 图像处理中边缘检测的VHDL源代码,所用的算法是garbor变换-Image processing edge detection of VHDL source code, the algorithms used are garbor transform
Platform: | Size: 384000 | Author: 翁文天 | Hits:

[VHDL-FPGA-Verilog] VHDLprogram

Description: 含有各类寄存器，AD和DA转换器，各种算法，有限状态机，还些许组合逻辑电路设计代码-Containing various types of registers, AD and DA converters, a variety of algorithms, finite state machine, but also some combinational logic circuit design code
Platform: | Size: 1808384 | Author: zhouwenbin | Hits:

[VHDL-FPGA-Verilog] svc_timer33ms

Description: Verilog 下脉冲发生器的源代码，可用于模拟三相交流电过零点，主要用于调试一些类似SVC（无功补偿）控制器的一些算法-Pulse generator under the Verilog source code, can be used to simulate three-phase alternating current zero-crossing point, mainly for debugging similar SVC (reactive power compensation) controller of a number of algorithms
Platform: | Size: 763904 | Author: huangyongbing | Hits:

[Communication] Turbo

Description: 利用3GPP交织器和LTE交织器完成turbo码的仿真并做比较，不同解码算法的比较-Using 3GPP Interleaver and complete LTE interleaver turbo code simulation and comparison, a comparison of different decoding algorithms
Platform: | Size: 112640 | Author: 老五 | Hits:

[Other] RTLHardwareDesignUsingVHDL

Description: Several unique features distinguish the book: * Coding style that shows a clear relationship between VHDL constructs and hardware components * Conceptual diagrams that illustrate the realization of VHDL codes * Emphasis on the code reuse * Practical examples that demonstrate and reinforce design concepts, procedures, and techniques * Two chapters on realizing sequential algorithms in hardware * Two chapters on scalable and parameterized designs and coding * One chapter covering the synchronization and interface between multiple clock domains -Several unique features distinguish the book: * Coding style that shows a clear relationship between VHDL constructs and hardware components * Conceptual diagrams that illustrate the realization of VHDL codes * Emphasis on the code reuse * Practical examples that demonstrate and reinforce design concepts, procedures, and techniques * Two chapters on realizing sequential algorithms in hardware * Two chapters on scalable and parameterized designs and coding * One chapter covering the synchronization and interface between multiple clock domains
Platform: | Size: 28478464 | Author: chane | Hits:

[Program doc] DSP--base--on-FPGA

Description: 这是一本国外的经典教材，讲述了现阶段所有数字信号处理的FPGA实现，从第二章讲述二进制的算法到现阶段数字信号处理的研究热点，基于FPGA实现！包括FIR，自适应滤波，纠错码，调制解调，加密，傅立叶变换等等。更难能可贵的是每个例子都有VHDL和Verilog代码-This is a classic foreign materials, described at this stage all the digital signal processing FPGA, from the second chapter about the binary digital signal processing algorithms to the current stage of research focus, based on FPGA implementation! Including FIR, adaptive filtering, error-correcting codes, modulation and demodulation, encryption, Fourier transform and so on. Even more valuable is that each case has a VHDL and Verilog code! !
Platform: | Size: 7067648 | Author: 刘伟 | Hits:

[Books] Errorcontrolcoding

Description: 信道编码非常有用的一本书，可以供通信方面的参考一下-　A reorganized and comprehensive major revision of a classic book, this edition provides a bridge between introductory digital communications and more advanced treatment of information theory. Completely updated to cover the latest developments, it presents state-of-the-art error control techniques. Coverage of the fundamentals of coding and the applications of codes to the design of real error control systems. Contains the most recent developments of coded modulation, trellises for codes, soft-decision decoding algorithms, turbo coding for reliable data transmission and other areas. There are two new chapters on Reed-Solomon codes & concatenated coding schemes. Also contains hundreds of new and revised examples and more than 200 illustrations of code structures, encoding and decoding circuits and error performance of many important codes and error control coding systems. Appropriate for those with minimum mathematical background as a comprehensive reference for coding theory.
Platform: | Size: 21752832 | Author: vidivici | Hits:

[VHDL-FPGA-Verilog] 20111122_4

Description: G711 defines two main compression algorithms, the µ -law algorithm (used in North America & Japan) and A-law algorithm (used in Europe and the rest of the world). The code provide codec in VHDL-G711 defines two main compression algorithms, the µ -law algorithm (used in North America & Japan) and A-law algorithm (used in Europe and the rest of the world). The code provide codec in VHDL
Platform: | Size: 13312 | Author: mpower | Hits:

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[Other] CORDIC-algorithms

[Graph program] DCT-vhdl

[VHDL-FPGA-Verilog] DA_FIR

[VHDL-FPGA-Verilog] huffman

[VHDL-FPGA-Verilog] quant

[VHDL-FPGA-Verilog] rle

[VHDL-FPGA-Verilog] zigzag_decode

[VHDL-FPGA-Verilog] edge

[VHDL-FPGA-Verilog] VHDLprogram

[VHDL-FPGA-Verilog] svc_timer33ms

[Communication] Turbo

[Other] RTLHardwareDesignUsingVHDL

[Program doc] DSP--base--on-FPGA

[Books] Errorcontrolcoding

[VHDL-FPGA-Verilog] 20111122_4

[VHDL-FPGA-Verilog] VGAtry

[Program doc] Simulation-of-VHDL-code

[VHDL-FPGA-Verilog] VHDL-and-Verilog

[Education soft system] Henson

[Embeded-SCM Develop] nai_vp62

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