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[SourceCode] altera sdram controller

Description: altera sdram controller vhdl
Platform: | Size: 2365413 | Author: langzhongfeilang@126.com | Hits:

[VHDL-FPGA-Verilog] pci_vhdl

Description: PCI的VHDL源码希望对大家有用！-PCI VHDL source hope useful for all!
Platform: | Size: 27648 | Author: 林建加 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776192 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] I2C总线控制器 altera提供-VHDL

Description: I2C总线控制器 altera提供的VHDL的源程序代码-I2C Bus Controller ALTERA the VHDL source code
Platform: | Size: 1639424 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] sdr sdram controller

Description: ALTERA sdram vhdl与verilog参考设计-Altera SDRAM VHDL and Verilog reference design
Platform: | Size: 2458624 | Author: 陈东平 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Altera的IP源码8237

Description: 名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-renowned name of the company Synopsys 8051IP Core VHDL language, support can be keilC51
Platform: | Size: 207872 | Author: 上面的 | Hits:

[VHDL-FPGA-Verilog] seq_gen_576

Description: 高清电视HDTV信号发生器，576P逐行，VHDL语言，ALTERA的Quartus II开发平台-HDTV HDTV signal generator, 576P progressive, VHDL, Altera's Quartus II development platform
Platform: | Size: 161792 | Author: lidan | Hits:

[Other] ref-ddr-sdram-vhdl

Description: 本程序是DDR SDRAM控制器的VHDL程序，由ALTERA 提供-this procedure is DDR SDRAM controller VHDL procedures provided by Altera
Platform: | Size: 437248 | Author: kevin | Hits:

[Communication] Project1-DDS

Description: 直接频率和成DDS，可以在Altera的FPGA下载实现-directly into DDS frequency and can be downloaded from Altera FPGA Implementation
Platform: | Size: 8192 | Author: lf | Hits:

[Embeded-SCM Develop] adda_spi

Description: 这个源码是用altera公司的开发工具NIOS II IDE开发的基于软核处理器的AD、DA控制程序，通过spi 核控制AD、DA的时序，实现正弦波发送和接收-this source is altera company development tools NIOS II IDE- based soft-core Office JIMMY of AD and DA control procedures, spi nuclear control AD and DA timetables to achieve sine sending and receiving
Platform: | Size: 66560 | Author: zeng xuan | Hits:

[VHDL-FPGA-Verilog] 8051_nios_vhdl

Description: 8051 MCU在nois平台上的实现代码（VHDL），出自Altera公司，经过严格测试核验证-nois 8051 MCU platform in the realization of code (VHDL) from Altera Corporation, after strict verification of nuclear test
Platform: | Size: 102400 | Author: 钟方 | Hits:

[Other] spi

Description: VHDL 实现的SPI接口，在Altera EMP7128 上应用过-VHDL SPI interface, the application of Altera EMP off
Platform: | Size: 1024 | Author: 陈同 | Hits:

[VHDL-FPGA-Verilog] cpu-leon3-altera-ep1c20

Description: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了在Altera公司的ep1c20 FPGA的位码文件和配置文件，可以直接下载使用！-A VHDL design with the use of powerful 32-bit CPU, this document contains Altera Corporation in the ep1c20 FPGA code and configuration files, you can direct download!
Platform: | Size: 687104 | Author: zhao onely | Hits:

[VHDL-FPGA-Verilog] cpu-leon3-altera-ep2s60-ddr

Description: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
Platform: | Size: 752640 | Author: zhao onely | Hits:

[Other] ALTERA-USB-BLASTER

Description: ALTERA-USB-BLASTER is a pdf file which is dawed by protel.
Platform: | Size: 18432 | Author: hewen1983 | Hits:

[MiddleWare] ram

Description: fpga中ram的vhdl的经典程序，适用于ALTERA公司器件-FPGA in VHDL ram the classic procedure, applicable to the company ALTERA devices
Platform: | Size: 1024 | Author: gcy | Hits:

[VHDL-FPGA-Verilog] ALTERA

Description: altera中文的器件选型手册，大家开发fpga采用altera的器件的话可以-altera Chinese manual device selection, the development of U.S. altera FPGA device used, then can
Platform: | Size: 706560 | Author: zhangxi | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram test controller altera -sdram test controller altera
Platform: | Size: 1519616 | Author: yangchun | Hits:

[ARM-PowerPC-ColdFire-MIPS] Altera

Description: 利用Nios Ⅱ软核处理器，以Altera公司的UP3开发板为硬件平台，以Quartus II、Quartus ID为软件开发平台，设计一个电子钟，实现下列系统功能： （1）在液晶屏上显示时间、日期、状态提示； （2）利用4个按键对时间（时分秒）、日期（年月日）进行设置； （3）利用一个LED灯指示当前设置状态；-The use of soft-core processor, Nios Ⅱ to Altera s UP3 development board as the hardware platform to Quartus II, Quartus ID for software development platform, design a clock
Platform: | Size: 6460416 | Author: Emma | Hits:

[VHDL-FPGA-Verilog] tdmddc_v61

Description: Designing Digital Down Conversion Systems with Altera CIC MegaCore and FIR Compensation Filter v6.1
Platform: | Size: 54272 | Author: | Hits:
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