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Description: 专门做处理器和周边接口的著名ipcore厂商CAST出品的UART H16550 ，包含完整的使用说明手册、testbench、可综合，如果被网站认可，将继续上传其余的几个更好的core。-specialized processor and peripheral interfaces famous ipcore CAST product manufacturers UART H16 550, including full use manual testbench can be integrated, if the site is approved, the rest will continue to upload a few better core.
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Size: 386048 |
Author: 宋云成 |
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Description: The UART (Universal Asynchronous Receiver/Transmitter) core provides serial
communication capabilities, which allow communication with modem or other external
devices, like another computer using a serial cable and RS232 protocol. This core is
designed to be maximally compatible with the industry standard National
Semiconductors’ 16550A device.
-The UART (Universal Asynchronous Receive r/Transmitter) core provides serial Communic ation capabilities, which allow communication with the modem or other e xternal devices, like another computer using a serial cable and R RS232 protocol. This core is designed to be maxim ally compatible with the industry standard Nat ional Semiconductors' 16550A device.
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Size: 187392 |
Author: 邓云 |
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Description: uart16550 ip core 通用异步收发器vhdl源代码-uart16550 ip core UART VHDL source code
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Size: 246784 |
Author: 姓名 |
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Description: Implements a 16550/16750 UART core
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Size: 100352 |
Author: Arun |
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Description: uart16550 is a 16550 compatible (mostly) UART core.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART:
FIFO based operation, interrupt requests and other.
The datasheet can be downloaded from the CVS tree along with the source code. -uart16550 is a 16550 compatible (mostly) UART core.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART:
FIFO based operation, interrupt requests and other.
The datasheet can be downloaded from the CVS tree along with the source code.
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Size: 1760256 |
Author: CloudZhang |
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Description: 开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character length, parity, stop bits and baud rate generator.
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Size: 1559552 |
Author: lisa1027 |
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Description: GM’s GM8180 MDC1 hardware environment is a highly efficient RISC-based platform for the purpose of
verifying and evaluating AMBA-based designs in the early development stage. The complete set of MDC1
GM8180 platform consists of a main board (MB120) equipped with GM8180 chip and an embedded GM
FA626 CPU.-Hardware:
Intel x86 compatible PC
Standard 16550 UART
Software:
Standard Linux distribution (Fedora core 2.6.14-FC5 or above)
FA626-based Linux distribution
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Size: 54044672 |
Author: 北科 |
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Description: 16550 uart code lattice cpld fpga 已经验证-16550 uart ip core
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Size: 713728 |
Author: zjc |
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Description: Implements a synthesizable 16550/16750 UART core.
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Size: 137216 |
Author: Juanjo |
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Description: 串口程序，基于16550内核，有不同的版本，比较齐全。-the UART program，based on 16550 core，have several versions。
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Size: 119808 |
Author: liming |
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Description: 实现一个一16750/16550 UART。该UART内核是完全基于另一个OpenCores的项目：UART_16750塞巴斯蒂安维特。
请找到有关于UART内核的文档。
该接口是现在有8位Wishbone总线兼容。
随着GHDL模拟器只需运行：
./ghdl_uart.bat
使用任何其他模拟器，开始模拟以下perl脚本必须运行之前：
uart_test_stim.pl> FILENAME.TXT
其中，FILENAME.TXT是通用的“stim_file”选择内部wb8_uart_transactor.vhd的名称。
正确的模拟应退出并断言消息“模拟END”。-Implements a 16550/16750 UART. The UART core is fully based on another OpenCores project: UART_16750 by Sebastian Witt.
Please find there the documentation regarding the Uart core.
The interface is now compatible with a 8-bit WishBone bus.
With GHDL simulator simply run:
./ghdl_uart.bat
Using any other simulator, before starting the simulation the following perl script must be run:
uart_test_stim.pl > filename.txt
where filename.txt is the name selected in generic stim_file inside wb8_uart_transactor.vhd.
A correct simulation should exit with an assertion message simulation END .
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Size: 21504 |
Author: 包 |
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Description: Using the UART core is the similar to using the standard 16550 UART, expect that the
FIFO’s are always enabled, and there is no sticky parity.
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Size: 131072 |
Author: 丁一 |
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Description: UART16550是16550兼容的UART核心（主要）。
总线接口是WISHBONE SoC总线启。B.
所有功能的标准选择16550 UART：FIFO的基础操作，要求和其他中断。
数据表可以下载从CVS树随着源代码-uart16550 is a 16550 compatible (mostly) UART core.
The bus interface is WISHBONE SoC bus Rev. B.
Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other.
The datasheet can be downloaded the CVS tree along with the source code
Platform: |
Size: 1545216 |
Author: asdtgg |
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