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[VHDL-FPGA-Verilog] uartverlog

Description: 占用资源少的verilog HDL uart接口；采用固定波特率115200，可以修改程序中的分频来修改波特率，模式为1个启始位，8位数据位，1个停止位；带1字节缓存；当缓存空时输出空信号-Occupy fewer resources verilog HDL uart interface adopted a fixed baud rate of 115200, can modify the procedure to modify the baud rate frequency, the model of a start bit, 8 data bits, 1 stop bit with one word section of the cache when the cache empty space-time output signal
Platform: | Size: 2048 | Author: 张诚 | Hits:

[VHDL-FPGA-Verilog] TLC549

Description: verilog TLC549AD采样程序 ，速度200K，在LED和数码管上显-verilog TLC549AD sampling procedures, the speed of 200K, in the LED and digital tube significantly
Platform: | Size: 1024 | Author: 张建中 | Hits:

[VHDL-FPGA-Verilog] tlc549verilog

Description: tlc549的verilog HDL程序，希望对大家有用-tlc549 the verilog HDL program, we hope to be useful
Platform: | Size: 1024 | Author: 飞星 | Hits:

[Other] ADtlc549_ctl

Description: 用Verilog HDL设计的TLC549 AD转换控制模块 -Design using Verilog HDL the TLC549 AD conversion control module
Platform: | Size: 65536 | Author: songsong | Hits:

[VHDL-FPGA-Verilog] tlc549adc

Description: 本程序是用Verilog HDL 状态机编写的tlc549的驱动程序-This procedure is used to write Verilog HDL state machine driver tlc549
Platform: | Size: 9216 | Author: zhangkui | Hits:

[VHDL-FPGA-Verilog] example14-ADC-ok

Description: 基于verilog HDL开发的ADC tlc549程序控制，已经调试通过。-Based verilog HDL developed ADC tlc549 control program has been adopted debugging.
Platform: | Size: 499712 | Author: lwb | Hits:

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