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[VHDL-FPGA-Verilog] MYCPU2.0

Description: 用verilog编写在FLEX10K上实现的简易CPU-used in the preparation of Verilog FLEX10K achieve simple CPU
Platform: | Size: 25600 | Author: 张桓铭 | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 这是一个Verilog HDL编写的RISC cpu的程序，该程序共10个子程序，实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu. Beginner can reference this example to study the Hardware discription language and the design manner. This program have passed the Modelsim validate.
Platform: | Size: 44032 | Author: 施向东 | Hits:

[Other Embeded program] sap1

Description: 這是用verilog寫的一個簡單的處理器，雖然只具有5個指令，但是可以透過這個範例，來了解到cpu的架構，與如何開發處理器，相信會有很大的啟發。-using Verilog This is a simple written by the processor, although with only five directives, through this example, to understand cpu architecture, how to develop processor, it would be very enlightening.
Platform: | Size: 33792 | Author: 吳中億 | Hits:

[Other] cpu的VERILOG描述

Description: RISC CPU的VerilogHDL描述-RISC CPU Verilog HDL description
Platform: | Size: 369664 | Author: 陈俊 | Hits:

[Algorithm] riscdesign

Description: 一个非常简单的cpu设计的原代码,是用verilog编写的-a very simple cpu design of the original code, was prepared by the Verilog
Platform: | Size: 730112 | Author: wanglei | Hits:

[VHDL-FPGA-Verilog] simple_cpu

Description: 初学cpu结构的很好的verilog代码的示例，适合初学者-novice cpu structure of the good verilog code examples for beginners
Platform: | Size: 79872 | Author: mapleni | Hits:

[VHDL-FPGA-Verilog] cpu

Description: Verilog实现的CPU程序，简单应用哈-Verilog realization of CPU process, simple application of Kazakhstan
Platform: | Size: 3072 | Author: liu | Hits:

[Windows Develop] simplecpu

Description: 一个16位简单CPU的Verilog源代码。-A CPU of 16 simple Verilog source code.
Platform: | Size: 79872 | Author: qiuyuwu | Hits:

[Other] RiscCpu

Description: Verilog-RISC CPU 代码 实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。 北航-Verilog-RISC CPU code to achieve a simple RISC cpu, a reference for beginners to learn the hardware description language, and design methods. The procedure adopted ModelSim simulation. BUAA
Platform: | Size: 9216 | Author: sss | Hits:

[VHDL-FPGA-Verilog] TINY3

Description: verilog 编写的tiny cpu 代码，可实现简单的指令和计算-Verilog prepared tiny cpu code, can be simple instructions and the calculation
Platform: | Size: 1660928 | Author: songbo | Hits:

[VHDL-FPGA-Verilog] verilog_design_a_simple_cpu

Description: 用verilog设计一个简单的cpu系统-Verilog design with a simple cpu system
Platform: | Size: 730112 | Author: jiangp | Hits:

[VHDL-FPGA-Verilog] cpu_lynn

Description: Verilog 实现的 简单 单线程 CPU， 基于计算机组成书目， 思路清晰， 有测试平台。-Verilog realization of a simple single-threaded CPU, the composition of computer-based bibliography, clear lines of thought, a test platform.
Platform: | Size: 11264 | Author: wei | Hits:

[VHDL-FPGA-Verilog] CPU

Description: verilog实现的一个简单的CPU，大家可下载去瞅瞅啊-verilog to achieve a simple CPU, you can download to Chou Chou ah
Platform: | Size: 5705728 | Author: zhangrongfei | Hits:

[VHDL-FPGA-Verilog] cpu

Description: verilog编写的简单的CPU，用于参考，已经过仿真-verilog prepared by a simple CPU, for reference, has been simulation
Platform: | Size: 4096 | Author: 于水洋 | Hits:

[Other Embeded program] RISCCPU

Description: 简单的CPU设计流程PPT，用于教学目的，可综合的verilog HDL设计。-A simple CPU design process PPT, for teaching purposes, can be integrated verilog HDL design.
Platform: | Size: 156672 | Author: 柳泽明 | Hits:

[VHDL-FPGA-Verilog] PipelineCPU

Description: 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
Platform: | Size: 28672 | Author: Matgek | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 实现了简单的CPU功能 采用三级流水线和超标量-CPU functions to achieve a simple three-stage pipeline and superscalar
Platform: | Size: 1735680 | Author: era | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 简单的cpu，以verilog语言写的，希望大家能提点意见。-Simple cpu, the verilog language to write, and I hope we can Tidianyijian.
Platform: | Size: 79872 | Author: 书柬图章 | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
Platform: | Size: 931840 | Author: 姜涛 | Hits:
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