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[Other resource] risc_cpu

Description: 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块
Platform: | Size: 814814 | Author: 瑞翔 | Hits:

[Other resource] RISC_CPU

Description: RISC CPU IP CORE 可以用于直接的工程开发应用 有详细的说明书
Platform: | Size: 574869 | Author: 毋杰 | Hits:

[Other resource] 16bit_cpu

Description: 16位的RISC_CPU， 应该对大家有帮助
Platform: | Size: 439977 | Author: ekin | Hits:

[Other resource] risc_cpu

Description: 这是一个Verilog HDL编写的RISC cpu的程序，该程序共10个子程序，实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu. Beginner can reference this example to study the Hardware discription language and the design manner. This program have passed the Modelsim validate.
Platform: | Size: 44088 | Author: 施向东 | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 这是一个Verilog HDL编写的RISC cpu的程序，该程序共10个子程序，实现了简单的RISC cpu，可供初学者参考，学习硬件描述语言，及设计方法。该程序通过了modelsim仿真验证。-This is the RISC cpu code which writed by Verilog HDL.This code has ten subprogram which came true the simple RISC cpu. Beginner can reference this example to study the Hardware discription language and the design manner. This program have passed the Modelsim validate.
Platform: | Size: 44032 | Author: 施向东 | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块-8-bit risc cpu the preparation, use the Quartus software to write, which built-in multiplier, divider modules
Platform: | Size: 814080 | Author: 瑞翔 | Hits:

[VHDL-FPGA-Verilog] RISC_CPU

Description: RISC CPU IP CORE 可以用于直接的工程开发应用 有详细的说明书-RISC CPU IP CORE can be used to direct the development and application of the project has a detailed brochure
Platform: | Size: 574464 | Author: 毋杰 | Hits:

[VHDL-FPGA-Verilog] 16bit_cpu

Description: 16位的RISC_CPU， 应该对大家有帮助-16 of RISC_CPU, everyone should have to help
Platform: | Size: 439296 | Author: ekin | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 此代码能高速实算术逻辑单元的功能，适合risc_CPU的设计。若有不足，请多多包含。-This code can be really high-speed arithmetic logic unit function, suitable for risc_CPU design. If insufficient, please contain.
Platform: | Size: 1024 | Author: 张朝阳 | Hits:

[source in ebook] XiaYuWen_8_RISC_CPU

Description: 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶化，综合时很可能会setup vio的，所以觉得直接用clk的上升沿来触发各个module比较好-XIA Yu-Wen 8 RISC_CPU complete code+ TESTBENCH (has debug) modelsim project documents, including the book by the three test procedures and related data, the absolute available ~ all signals were found in compliance with the original name. Not found in the forums Testbench, and there is only one mcu code, but many and the book is not the same as he changed a lot of support under the U.S. ~````` ah ~ `I think the book is still some uncertainty unsatisfactory places, such as clk_gen.v in clk2, clk4 is of no use, assign clk1 = ~ clk reuse CLK1 of negedge clk1 to trigger module is not all good, cause the deterioration of timing, synthesis is likely to setup vio, therefore, feel that the direct use of the rising edge of clk to trigger each module is better
Platform: | Size: 86016 | Author: 刘志伟 | Hits:

[OS program] CPU

Description: cpu累加器。主要用于在RISC_CPU设计中的累加器module中，同时还包含cpu的其他模块-cpu accumalation
Platform: | Size: 113664 | Author: majiajun | Hits:

[DSP program] risc_cpu

Description: This an example of simple RISC CPU implemented in SystemC.-This is an example of simple RISC CPU implemented in SystemC.
Platform: | Size: 41984 | Author: R Zhang | Hits:

[VHDL-FPGA-Verilog] RISC_CPU

Description: Verilog HDL编写的一个精简指令的处理器，很好用，可用来学习-Verilog HDL RISC_CPU
Platform: | Size: 14336 | Author: | Hits:

[SCSI-ASPI] 115157712RISC8

Description: RISC_CPU 包含基本行为模块和测试模块-RISC_CPU contains basic behavior modules and test modules
Platform: | Size: 4534272 | Author: cc | Hits:

[VHDL-FPGA-Verilog] RISC_CPU

Description: Verilog写的简单处理器QuartusII下可编译 //指令 操作码 源寄存器 目的寄存器 操作 // NOP 0000 xxxxx xxxxxx 空操作 //ADD 0001 src dest dest<=src+dest //SUB 0010 src dest dest<=dest-src //AND 0011 src dest dest<=src&&dest //NOT 0100 src dest dest<=~src //RD 0101 xxxxx dest dest<= memory[Add_R] //WR 0110 src xxxxx memory[Add_R]<=src //BR 0111 xxxxx xxxxx PC<=memory[Add_R] //BRZ 1000 xxxxx xxxxx PC<=memory[Add_R] //HALT 1111 xxxxx xxxxx 挂起至RST-Verilog写的简单处理器QuartusII下可编译 //指令 操作码 源寄存器 目的寄存器 操作 // NOP 0000 xxxxx xxxxxx 空操作 //ADD 0001 src dest dest<=src+dest //SUB 0010 src dest dest<=dest-src //AND 0011 src dest dest<=src&&dest //NOT 0100 src dest dest<=~src //RD 0101 xxxxx dest dest<= memory[Add_R] //WR 0110 src xxxxx memory[Add_R]<=src //BR 0111 xxxxx xxxxx PC<=memory[Add_R] //BRZ 1000 xxxxx xxxxx PC<=memory[Add_R] //HALT 1111 xxxxx xxxxx 挂起至RST
Platform: | Size: 328704 | Author: 魏文沫 | Hits:

[VHDL-FPGA-Verilog] RISC_CPU

Description: VHDL语言设计的RISC_CPU，分为八个基本部件分模块构建，分别为时钟发生器，指令寄存器，累加器，算术逻辑运算单元，数据控制器，状态控制器，程序计数器以及地址多路器-The VHDL language RISC_CPU, is divided into eight basic components of modular construction, respectively, the clock generator, the instruction register, accumulator, arithmetic and logic unit, the data controller, the state controller, the program counter and address multiplexer
Platform: | Size: 6144 | Author: 林琳 | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: RISC_cpu，包括所有的模块与测试文件。是夏宇闻第二版书中的错误均已改正，运行正确后上传，请放心使用。-RISC_cpu, including all modules and test files. Xia Wen error of the second edition of the book have been correct, to run correctly upload, please feel free to use.
Platform: | Size: 6144 | Author: 王骁蒙 | Hits:

[VHDL-FPGA-Verilog] 8-bit-RISC_CPU

Description: 8位RISC_CPU设计的verilog源码以及工程文件、测试数据文件。在modelsim 10.1d下验证成功，打开工程文件即可使用。-8 RISC_CPU design verilog source code and project files, test data files. In modelsim 10.1d validation is successful, open the project file can be used.
Platform: | Size: 190464 | Author: | Hits:

[VHDL-FPGA-Verilog] RISC_CPU

Description: 这是用verilog写的一个基于状态机的简易RISC_CPU的设计，里面包含各个模块，每个模块经过仿真没有问题，整个工程在板子上经过试验。-This is a verilog to write a simple RISC_CPU based state machine design, which contains various modules, each module through simulation without problems, the whole project tested on the board
Platform: | Size: 1121280 | Author: 冯永帅 | Hits:

[assembly language] RISC_CPU

Description: RISC_CPU 设计练习这是用verilog写的一个基于状态机的简易RISC_CPU的设计，里面包含各个模块，每个模块经过仿真没有问题，整个工程在板子上经过试验。--This is a verilog to write a simple RISC_CPU based state machine design, which contains various modules, each module through simulation without problems, the whole project tested on the board
Platform: | Size: 1556480 | Author: Dong | Hits:
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