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[Other resource] PCI

Description: PCI设计指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented PCI Bus interface. This interface is available in 32-bit and 64- bit versions, with support for multiple Xilinx FPGA device families. It is designed to support both Verilog-HDL and VHDL. The design examples in this book are provided in Verilog.
Platform: | Size: 899078 | Author: lee | Hits:

[Other] PCI_Target_ip

Description: pci core altera fpga pci开发设计资料-pci core altera fpga development of design information pci
Platform: | Size: 428032 | Author: zhouhong | Hits:

[ELanguage] usb_funct

Description: USB接口的VHDL源码，支持Verilog HDL程序-USB VHDL source code, supports Verilog HDL procedures
Platform: | Size: 230400 | Author: 王森 | Hits:

[VHDL-FPGA-Verilog] pci_express_crc

Description: PCI express CRC rtl core for Fpga/asic Designer
Platform: | Size: 202752 | Author: 李晓媛 | Hits:

[Other] PCI

Description: PCI设计指南The Xilinx LogiCORE PCI interface is a fully verified, pre-implemented PCI Bus interface. This interface is available in 32-bit and 64- bit versions, with support for multiple Xilinx FPGA device families. It is designed to support both Verilog-HDL and VHDL. The design examples in this book are provided in Verilog.-PCI Design Guide The Xilinx LogiCORE PCI interface is a fully verified, pre-implementedPCI Bus interface. This interface is available in 32-bit and 64-bit versions, with support for multiple Xilinx FPGA device families. Itis designed to support both Verilog-HDL and VHDL. The designexamples in this book are provided in Verilog.
Platform: | Size: 899072 | Author: lee | Hits:

[Other] lpcinterface

Description: lpc源代码verilog实现的。操作low pin count设备-LPC realize the Verilog source code. Operation of low pin count devices
Platform: | Size: 1024 | Author: 毛军捷 | Hits:

[File Format] asic_design

Description: 华为,大规模逻辑设计指导书,规格详细，包括：VHDL编写规范，Verilog编写规范，asic设计方法，同步电路设计规则，vhdl电路设计，代码可重用设计，-Huawei, a large-scale logic design guide books, detailed specifications, including: VHDL specification preparation, Verilog specification preparation, asic design, synchronous circuit design rules, vhdl circuit design, reusable code design,
Platform: | Size: 2041856 | Author: feng jee | Hits:

[VHDL-FPGA-Verilog] multi16

Description: verilog 写的两种方式的乘法器 不错!-Verilog write the multiplier in two ways good!
Platform: | Size: 7168 | Author: rayax | Hits:

[VHDL-FPGA-Verilog] arbiter

Description: 一个用verilog编写的总线仲裁程序。多个设备共享总线，不同设备的优先级是变化的，保证每个设备都有公平的使用总线的机会。-Verilog prepared a bus with arbitration proceedings. Multiple devices share the bus, the priority of different devices is changing to ensure that each device will have a fair opportunity to use the bus.
Platform: | Size: 3072 | Author: bao rui | Hits:

[VHDL-FPGA-Verilog] pci_t

Description: verilog开发的PCI target模块，能完成配置空间的读写以及单次的memory读写，原创。-Verilog development of PCI target module, to complete the reading and writing, as well as the configuration space of a single memory read and write, originality. Ha ha
Platform: | Size: 10240 | Author: 齐培红 | Hits:

[VHDL-FPGA-Verilog] PCI_arbi

Description: PCI arbi verilog source code
Platform: | Size: 3072 | Author: bulbul1225 | Hits:

[Embeded-SCM Develop] pci.tar

Description: verilog编写的PCI总线，提供了Wishbone bus和PCI local bus之间的接口，内由两个独立的模块组成，分别完成WB BUS和PCI bus之间的传输-The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transactions originating on the PCI bus, the other one handling transactions originating on the WISHBONE bus.
Platform: | Size: 13253632 | Author: yemao | Hits:

[Embeded-SCM Develop] FPGA-PCI

Description: 基于FPGA的PCI接口源代码及Testbench Verilog程序代码-fpag pci
Platform: | Size: 467968 | Author: lang | Hits:

[USB develop] pci-verilog

Description: USB及PCI总线设计的一些源代码（经测试）-USB and PCI bus design some of the source code
Platform: | Size: 431104 | Author: tom | Hits:

[VHDL-FPGA-Verilog] pci_32tlite_oc

Description: 嵌入式 pci总线IP core的rtl源代码，用Verilog实现-Embedded pci bus IP core of the rtl source code, Verilog realization of
Platform: | Size: 3941376 | Author: 陈达燕 | Hits:

[VHDL-FPGA-Verilog] PCI9052

Description: 用verilog语言编译的pci协议实现，而且有具体的电路图-Compiled with the verilog language pci protocol implementation, but also the specific circuit
Platform: | Size: 1941504 | Author: 李超 | Hits:

[source in ebook] pci_target

Description: pci target design verilog file
Platform: | Size: 53248 | Author: peter | Hits:

[VHDL-FPGA-Verilog] sdram_pci

Description: 基于SDRAM的PCI采集程序，PCI9054控制器+SDRAM控制器Verilog源代码，，已经SignalTap调试通过。-SDRAM PCI-based acquisition program, PCI9054 Controller+ SDRAM controller Verilog source code, has SignalTap through debugging.
Platform: | Size: 3166208 | Author: wangbo | Hits:

[VHDL-FPGA-Verilog] Verilog-pci

Description: PCI的FPGA实现，使用verilog硬件描述语言模拟pci数据接口的数据传输过程。-PCI simulation with FPGA, using the verilog hardware describing language to simulate data transfer processes on pci data interface.
Platform: | Size: 5510144 | Author: zxc | Hits:

[VHDL-FPGA-Verilog] PCI-dio

Description: 基于PCI的DIO接口程序，包括verilog源程序、驱动源程序以及寄存器说明文件-PCI-DIO-based interface program, including the verilog source code, driver source code and documentation register
Platform: | Size: 2309120 | Author: zifeng | Hits:
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