Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - NIOS II s

Search list

[Embeded-SCM Develop] SIN_fashengqi

Description: 2006altera大赛－基于软核Nios的宽谱正弦信号发生器设计：摘要：本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA公司的 Cyclone 系列 FPGA 为数字平台，将微处理器、总线、数字频率合成器、存储器和 I/O 接口等硬件设备集中在一片 FPGA 上，利用直接数字频率合成技术、数字调制技术实现所要求波形的产生，用 FPGA 中的 ROM 储存 DDS 所需的波形表，充分利用片上资源，提高了系统的精确度、稳定性和抗干扰性能。使用新的数字信号处理（DSP）技术，通过在 Nios 中软件编程解决 不同的调制方式的实现和选择。系统频率实现 1Hz～20MHz 可调，步进达到了1Hz；完成了调幅、调频、二进制 PSK、二进制 ASK、二进制 FSK 调制和扫频输出的功能。 -2006altera race-based soft-core Nios wide spectrum of sinusoidal signal generator design : Abstract : The use of design-based Nios II embedded processor SOPC technology. Altera Corporation system to the Cyclone FPGA series of digital platform, microprocessor, bus, Digital Frequency Synthesizer, memory and I / O interface hardware concentrated in an FPGA, the use of direct digital frequency synthesis technology and digital modulation waveforms required to achieve the rise, Using FPGA ROM storage of the DDS waveform table, and make full use of on-chip resources, improve the system's accuracy, stability and robustness. Use of new digital signal processing (DSP) technology, Nios through software programming to solve different ways of achieving modulation and choice. Realize the system freq
Platform: | Size: 407706 | Author: 刘斐 | Hits:

[Embeded-SCM Develop] SIN_fashengqi

Description: 2006altera大赛－基于软核Nios的宽谱正弦信号发生器设计：摘要：本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA公司的 Cyclone 系列 FPGA 为数字平台，将微处理器、总线、数字频率合成器、存储器和 I/O 接口等硬件设备集中在一片 FPGA 上，利用直接数字频率合成技术、数字调制技术实现所要求波形的产生，用 FPGA 中的 ROM 储存 DDS 所需的波形表，充分利用片上资源，提高了系统的精确度、稳定性和抗干扰性能。使用新的数字信号处理（DSP）技术，通过在 Nios 中软件编程解决 不同的调制方式的实现和选择。系统频率实现 1Hz～20MHz 可调，步进达到了1Hz；完成了调幅、调频、二进制 PSK、二进制 ASK、二进制 FSK 调制和扫频输出的功能。 -2006altera race-based soft-core Nios wide spectrum of sinusoidal signal generator design : Abstract : The use of design-based Nios II embedded processor SOPC technology. Altera Corporation system to the Cyclone FPGA series of digital platform, microprocessor, bus, Digital Frequency Synthesizer, memory and I/O interface hardware concentrated in an FPGA, the use of direct digital frequency synthesis technology and digital modulation waveforms required to achieve the rise, Using FPGA ROM storage of the DDS waveform table, and make full use of on-chip resources, improve the system's accuracy, stability and robustness. Use of new digital signal processing (DSP) technology, Nios through software programming to solve different ways of achieving modulation and choice. Realize the system freq
Platform: | Size: 407552 | Author: 刘斐 | Hits:

[Embeded-SCM Develop] hello_world_0

Description: 此源码是用altera公司的nios II IDE开发的，基于DE2核心板的SD卡播放wav格式音频文件的程序-This source is altera s nios II IDE development, based on the core DE2 board SD card playback wav format audio files
Platform: | Size: 144384 | Author: zeng xuan | Hits:

[Embeded-SCM Develop] Binary_VGA_Controller

Description: VGA的IP核，可直接用于nios II的应用里，在DE2板子直接使用-VGA s IP core, can be used directly in nios II applications, the direct use in the DE2 board
Platform: | Size: 79872 | Author: 沈克镇 | Hits:

[Embeded-SCM Develop] ISP1362

Description: ISP1362的IP核，可直接用于nios II的应用里，在DE2板子直接使用-ISP1362 s IP core, can be used directly in nios II applications, the direct use in the DE2 board
Platform: | Size: 18432 | Author: 沈克镇 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Altera

Description: 利用Nios Ⅱ软核处理器，以Altera公司的UP3开发板为硬件平台，以Quartus II、Quartus ID为软件开发平台，设计一个电子钟，实现下列系统功能： （1）在液晶屏上显示时间、日期、状态提示； （2）利用4个按键对时间（时分秒）、日期（年月日）进行设置； （3）利用一个LED灯指示当前设置状态；-The use of soft-core processor, Nios Ⅱ to Altera s UP3 development board as the hardware platform to Quartus II, Quartus ID for software development platform, design a clock
Platform: | Size: 6460416 | Author: Emma | Hits:

[Other] NiosII_Software_Developers_Handbook

Description: Nios II Software Developer’s Handbook-Nios II Software Developer s Handbook
Platform: | Size: 2072576 | Author: yingjiang | Hits:

[VHDL-FPGA-Verilog] tut_DE2_sdram_vhdl

Description: This tutorial explains how the SDRAM chip on ltera’s DE2 Development and Education board can be used with a Nios II system implemented by using the Altera SOPC Builder.
Platform: | Size: 546816 | Author: *Roma* | Hits:

[VHDL-FPGA-Verilog] NiosII_Software_Developer_Handbook

Description: Nios II Software Developer s Handbook Nios II软件部分开发手册 也可以到Altera官方网上下载-Nios II Software Developer s Handbook
Platform: | Size: 1648640 | Author: weiw | Hits:

[VHDL-FPGA-Verilog] ds18b20

Description: 这是基于NIOS II的 DS18B20 的源码，绝对可用本人已经调试成功，希望对大家有-It s a DS18B20 code for nios ii.
Platform: | Size: 1673216 | Author: tom | Hits:

[SCM] LED

Description: 本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA 公司的 Cyclone II 系列 FPGA 为数字平台，将微处理器、Avalon 总线、LED 点阵扫描控制器、存储器和人机接口控制器等硬件设备集中在一片 FPGA 上，利用片内硬件来实现 LED 点阵的带地址扫描，降低系统总功耗和简化 CPU 编程的同时，提高了系统的精确度、稳定性和抗干扰性能。-This design used the Nios II embedded processor based on SOPC technology. System to ALTERA' s Cyclone II series FPGA for digital platforms, microprocessors, Avalon bus, LED dot matrix scan controller, memory and man-machine interface controller and other hardware devices focused on an FPGA, using on-chip hardware to achieve the LED dot-matrix band address scan, reducing the total system CPU power consumption and simplify programming while increasing the system' s accuracy, stability and anti-jamming performance.
Platform: | Size: 968704 | Author: 叶子 | Hits:

[VHDL-FPGA-Verilog] Nios_II_SPI

Description: 本源码为Nios II的开发示例,主要演示Nios II的SPI总线设计。开发环境QuartusII。 本示例十分经典，对基于SOPC开发的FPGA初学者有很大帮助。-The source code for the Nios II development of an example, the main demonstration Nios II design of the SPI bus. Development environment QuartusII. This example is very classic, FPGA-based SOPC development of great help for beginners.
Platform: | Size: 16035840 | Author: huangshengqun | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAMDesignTutorials

Description: Altera公司的基于NIOSII设计DDR和DDR2内存的资料，很有帮助的，-Based on Altera' s DDR and DDR2 memory NIOSII design information, useful,
Platform: | Size: 3154944 | Author: iyoung | Hits:

[VHDL-FPGA-Verilog] LED-DISPLAY

Description: 在DE2板上 （nios II）实现LED的年月日，时分秒的显示。-Achieving LED s year, month, day, hour, minute, seconds display in the DE2 board (nios II).
Platform: | Size: 1024 | Author: zhangxin | Hits:

[VHDL-FPGA-Verilog] High-Speed-FFT

Description: 优秀硕士论文，课题采用现场可编程门阵列((FPGA)，设计实现了一种超高速FFT处理器。目前，使用FPGA实现FFT多采用基2和基4结构，随着FPGA规模的不断扩大，使采用更高基数实现FFT变换成为可能。本课题就是采用Alter的Stratix II芯片完成了基16-FFT处理器的设计。在设计实现过程中，以基2-FFT搭建基16-FFT的运算核，合理安排时序，解决了碟形运算、数据传输和存储操作协调一致的问题。由于采用流水线工作方式，使整个系统的数据交换和处理速度得以很大提高。本设计实现了4096点和256点的变换，两个内部运算时钟都可以达到1 OOMHz以上，其中256点变换的数据吞吐率高达1.36GHz -a design of ultra high speed FFT processor based onFPGA is developed in this paper. At present we always use radix-2 and radix-4 tocarry out FFT. When the scale of FPGA is panding,it s possible to implement higher radix FFT. This topic uses Stratix II of Altera company to carry out a processor of radix一16 FFT.In this design, radix-16 FFT is carried out by radix-2FFT, The design uses rational time sequence arrangement to make butterflycomputing,data transformation and memory coincide.In order to avoid the bottleneck,pipeline pattern is used,this method acceletates the operating.Thescheme realizes the 4096-points and 256-points FFT, their operation clocks canboth reach above 100MHz. Among them ,the throughput of 256-points FFT is up to1.36GHz.
Platform: | Size: 3759104 | Author: 陈子牙 | Hits:

[SCM] sd_card

Description: 面向altera公司的大学计划sd-card ip核，检测sd卡是否插入卡槽中。-Altera company s University Program for sd-card ip core, testing sd card is inserted into the card slot
Platform: | Size: 1643520 | Author: 陈小林 | Hits:

[Embeded-SCM Develop] s

Description: 黑金板NIOS II的代码全集对于NIOS 2初学者很有帮助-NIOS II code black gold plate for the NIOS 2 Complete beginners helpful. . . . . . . . . . . .
Platform: | Size: 124928 | Author: 李球 | Hits:

[VHDL-FPGA-Verilog] Qsys_nios2

Description: 本教程使用最新的Quartus 11.0sp1+Nios 11.0sp1开发工具。在最新的Quartus II软件中，使用了全新的Qsys进行SOPC系统的构建。 较之以前版本使用SOPC Builder构建有了很大的不同。 本教程为Altera最新的官方Tutorial。 一步步教你使用Qsys构建Nios II系统，并使用Nios II SBT开发应用程序。-This tutorial uses the latest Quartus 11.0sp1+ Nios 11.0sp1 development tools. In the latest Quartus II software, the use of a new build Qsys the SOPC system. Than the previous version has been using the SOPC Builder to build a big difference. This tutorial Altera' s latest official Tutorial. Step by step to teach you to use Qsys build Nios II system, and use the Nios II SBT application development.
Platform: | Size: 2358272 | Author: | Hits:

[VHDL-FPGA-Verilog] DE2_115_SD_CARD

Description: DE2_115开发板给出的基于NIOS的SD卡的实例-DE2-115 nios ii s vhdl
Platform: | Size: 2336768 | Author: 姚挺 | Hits:

[Embeded-SCM Develop] NIOS-II常用函数详解

Description: Nios II系列软核处理器是Altera的第二代FPGA嵌入式处理器，其性能超过200DMIPS，。Altera的Stratix 、Stratix GX、 Stratix II和 Cyclone系列FPGA全面支持Nios II处理器，以后推出的FPGA器件也将支持Nios II。(The Nios II family of soft core processors is the second generation of Altera's FPGA embedded processor that provides support for Altera's Stratix, Stratix GX, Stratix II, and Cyclone FPGA families that exceed 200DMIPS in performance.)
Platform: | Size: 74752 | Author: 彩云之南7 | Hits:
« 12 3 »

CodeBus www.codebus.net