Search - Mentor Graphics

[Other resource] Des2Sim

Description: 本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1； Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。
Platform: | Size: 1945930 | Author: 黄鹏曾 | Hits:

[Develop Tools] Mentor Graphics

Description: mentorGraphics公司产品资料-mentorGraphics product information
Platform: | Size: 5227717 | Author: 彭明 | Hits:

[Books] Mentor Graphics

Description: mentorGraphics公司产品资料-mentorGraphics product information
Platform: | Size: 5227520 | Author: 彭明 | Hits:

[Special Effects] 20060320001-5580

Description: 导师给的关于图像图像处理的源代码，也是图形检测的！-mentor to the image processing images on the source code, as well as detection of graphics!
Platform: | Size: 2409472 | Author: oyjerry | Hits:

[OpenGL program] OpenGL_Wizard

Description: 在ＶＣ２００３中结合ＯpenGL实现绘图功能，是初学者的良师．值得看看.-In VC2003 realize the integration of OpenGL graphics, is the mentor for beginners. Worthwhile to see.
Platform: | Size: 1113088 | Author: 罗海燕 | Hits:

[VHDL-FPGA-Verilog] Des2Sim

Description: 本文介绍了一个使用 VHDL 描述计数器的设计、综合、仿真的全过程，作为我这一段时间自学 FPGA/CPLD 的总结，如果有什么不正确的地方，敬请各位不幸看到这篇文章的大侠们指正，在此表示感谢。当然，这是一个非常简单的时序逻辑电路实例，主要是详细描述了一些软件的使用方法。文章中涉及的软件有Synplicity 公司出品的Synplify Pro 7.7.1； Altera 公司出品的 Quartus II 4.2；Mentor Graphics 公司出品的 ModelSim SE 6.0。 -This article describes a VHDL description of the use of counter design, synthesis, simulation of the entire process, this time as my self-FPGA/CPLD summary, if what has not the right place, please see this article that, unfortunately, the heroes They correct me, wish to express my gratitude. Of course, this is a very simple example of sequential logic circuit is mainly a detailed description of a number of software usage. Article involved in the software company has produced Synplicity
Platform: | Size: 1945600 | Author: 黄鹏曾 | Hits:

[Compress-Decompress algrithms] huffman_Golomb_COMPRESS

Description: 从 Mentor Graphics 的自动测试图形生成（ATPG）工具 FastScan的测试文档中提取出测试电路（CUT）的测试模式，生成便于对应压缩算法的文件格式。本文中，给出了 2 种压缩测试模式的方法，一种是基于统计的哈夫曼编码，一种是基于差分运算的Golomb 编码。本次毕业设计中，在熟悉Mentor Graphics ATPG工具 FastScan的基本功能和其主要的测试模式输出文件的格式的基础上，实现其中测试结构和测试模式数据的分析提取，并且在掌握典型的测试模式压缩算法的思想以及 C/C++开发环境的前提下，选择或综合相关的优化压缩算法，针对测试结构信息，实现测试模式数据的压缩，及软件的基本图形化操作和结果报告界面。 -the scheme of the tested circuits is extracted from the test documents of FastScan, a tool of Automatic Test Pattern Generator of Mentor Graphcis, and translated into a form processed by the compressing algorithm. The paper proposes two methods for compressing tested pattern, one based on statistical Huffman Code, the other based on differential Golomb code. Based on the function of Mentor Graphics ATPG and the format of output file of the test pattern, the program extracts and analyzes of the tested structure and data pattern familiar with typical compressing algorithm and C/C++ developing environments, the program selects and synthesizes the relevant optimal compressing algorithm, successfully compresses the test pattern data related with the structural information, and implements the graphical interactive interface and a report form of the result.
Platform: | Size: 6144 | Author: 张志刚 | Hits:

[Technology Management] ICdesigntools

Description: IC设计工具很多，其中按市场所占份额排行为Cadence、Mentor Graphics和Synopsys。-IC design tools, many of them ranked by market share for Cadence, Mentor Graphics and Synopsys.
Platform: | Size: 5120 | Author: 蒋阳 | Hits:

[Software Engineering] EDGE_brochure

Description: EDGE DEVELOPER SUITE - Mentor Graphics EDGE™ Developer Suite comprises a comprehensive set of software-EDGE DEVELOPER SUITE- Mentor Graphics EDGE™ Developer Suite comprises a comprehensive set of software
Platform: | Size: 920576 | Author: culinor | Hits:

[VHDL-FPGA-Verilog] jop

Description: ALL VHDL FPGA -- THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF -- MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
Platform: | Size: 2789376 | Author: sungkoo | Hits:

[VHDL-FPGA-Verilog] ic_design_flow_vhdl

Description: vhdl code and icdesign flow for mentor graphics ic design tools
Platform: | Size: 129024 | Author: kamran | Hits:

[Other] icdesign_tutorial

Description: ic design tutorials for mentor graphics
Platform: | Size: 2108416 | Author: kamran | Hits:

[Embeded-SCM Develop] EE2007.7

Description: EE2007.7的种子，可以下载！也可以链接这个网站下载http://www.ebookee.net/Mentor-Graphics-Expedition-Enterprise-Flow-v-EE2007-7_500337.html-Mentor Graphics Expedition Enterprise Flow v.EE2007.7
Platform: | Size: 12288 | Author: 刘新华 | Hits:

[VHDL-FPGA-Verilog] modelsim_cmd_ref_ug

Description: Mentor Graphics ModelSim Reference Manual Software v6.3g。图形界面Modelsim仿真说明手册，对工具及命令说明非常详细。官方资料-Mentor Graphics ModelSim Reference Manual Software v6.3g. Graphical interface Modelsim simulation instruction manual, instructions on the tools and commands are very detailed. Official information
Platform: | Size: 658432 | Author: Jasking Wu | Hits:

[VHDL-FPGA-Verilog] modelsim_ug

Description: Mentor Graphics ModelSim User s Guide Software v6.3g。ModelSim的用户指导书，对于Modelsim入门非常有用，堪称是手把手交了。官方资料，绝对可靠！-Mentor Graphics ModelSim User' s Guide Software v6.3g. ModelSim' s user guide book is very useful for Modelsim entry, perhaps the most hands-handed. Official information, absolutely reliable!
Platform: | Size: 2214912 | Author: Jasking Wu | Hits:

[SCM] bmp2asc

Description: BMP to ASC converter for mentor graphics PADS
Platform: | Size: 14336 | Author: tirthraj | Hits:

[VHDL-FPGA-Verilog] Modelsim--script-usage

Description: modelsim是Mentor graphics公司推出的HDL代码仿真工具，也是业界最流行的HDL仿真工具之一。支持图形界面操作和脚本操作。常见的图形界面操作相对直观，但是由于重复性操作几率高、处理效率低、工程的非保存性，对于大规模的代码仿真不推荐使用；脚本操作完全可以克服以上的缺点，把常见的命令，比如库文件和RTL加载、仿真、波形显示等命令编辑成.do脚本文件，只需要让Modelsim运行.do文件即可以完成仿真，智能化程度高。本文重点介绍Modelsim常见命令的使用，以及如何使用.do文件进行智能化的仿真。参考文档：PKT.rar -Modelsim is a very popular tool for simulating the verilog language and debugging. This paper focus to tell the basic script of modelsim and it can help to greatly improve our dugging efficency..
Platform: | Size: 374784 | Author: liangyao | Hits:

[VHDL-FPGA-Verilog] Counter-60

Description: In this example, counter 60 is implemented as part of the real time clock time electronic clocks. Done in the platform mentor Graphics and describes in the VHDL code. This counter has a role to the front edge of every 60 clock sends a signal following the counter.
Platform: | Size: 3956736 | Author: Milos | Hits:

[SCM] Mentor-mod

Description: 内容纯正，PCB原版教程包含Mentor Graphics EE等一些主流电路版图教程-Content is pure, the original tutorial
Platform: | Size: 193536 | Author: 晚景 | Hits:

[SCM] Mentor(WG2007.5)_Super-Crack

Description: Mentor.Graphics.Expedition.Enterprise.Flow.v2007.5破解文件,详细破解方法以及非常齐全的库文件-Mentor.Graphics.Expedition.Enterprise.Flow.v2007.5 Crack And Library
Platform: | Size: 9071616 | Author: markytwine | Hits:

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