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[VHDL-FPGA-VerilogISP1362

Description: Verilog 编写的ISP1362的控制器IP核,altera公司DE2系统中的源程序-Verilog prepared ISP1362 controller IP core, altera company source DE2 System
Platform: | Size: 18432 | Author: zhyy | Hits:

[USB developisp1362_g

Description: 网上收集的利用nios软核,使用isp1362芯片开发的u盘程序,有助于usb开发的理解和ufi协议的理解。已经验证,完全可用xp自带驱动。-Collected online using Nios soft-core, use isp1362 chip development process u disk, usb help develop the understanding and agreement ufi understanding. Has been verified, fully available to bring their own driver xp.
Platform: | Size: 15360 | Author: manual | Hits:

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