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[Static control] clock2001

Description: 时钟模块之一：二进制转BCD码verilog源代码FPGA advantage编程环境-clock module : BCD switch binary source code Verilog FPGA advantage programming environment
Platform: | Size: 822 | Author: dandan | Hits:

[Other resource] verlog_basic

Description: 用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器，乘法器，除法器，多路选择器，二进制转BCD码，加法器，减法器等等。-verlog used some language addendum to the basic experiment, which is suitable for FPGA / CPLD beginners. Including eight priority encoder, multipliers, dividers, multi-path selectors, binary switch BCD, adder, subtraction, and so on.
Platform: | Size: 1004071 | Author: leolili | Hits:

[Other] BCDencode

Description: 这是一个FPGA的BCD码编码器设计.编译后可以下载到ALTEA的器件中仿真.
Platform: | Size: 114713 | Author: 童永强 | Hits:

[Static control] clock2001

Description: 时钟模块之一：二进制转BCD码verilog源代码FPGA advantage编程环境-clock module : BCD switch binary source code Verilog FPGA advantage programming environment
Platform: | Size: 1024 | Author: dandan | Hits:

[VHDL-FPGA-Verilog] verlog_basic

Description: 用verlog语言编的一些基础实验,适合于FPGA/CPLD的初学者。内容包括8位优先编码器，乘法器，除法器，多路选择器，二进制转BCD码，加法器，减法器等等。-verlog used some language addendum to the basic experiment, which is suitable for FPGA/CPLD beginners. Including eight priority encoder, multipliers, dividers, multi-path selectors, binary switch BCD, adder, subtraction, and so on.
Platform: | Size: 1004544 | Author: leolili | Hits:

[Other] BCDencode

Description: 这是一个FPGA的BCD码编码器设计.编译后可以下载到ALTEA的器件中仿真.-This is a FPGA-BCD Encoder design. Compilers can be downloaded to the device simulation Altea.
Platform: | Size: 114688 | Author: 童永强 | Hits:

[Other] bcdto7seg

Description: this a code for converting bcd to 7segment in fpga IC-this is a code for converting bcd to 7segment in fpga IC
Platform: | Size: 2048 | Author: soheil | Hits:

[VHDL-FPGA-Verilog] HEX2BCD

Description: 基于fpga的二进制和BCD骂转换模块vhdl描述，只需修改相关参数即可使用-Fpga-based binary and BCD conversion module called vhdl description, simply modify the relevant parameters to use
Platform: | Size: 1024 | Author: 郭帅 | Hits:

[VHDL-FPGA-Verilog] Seven-Segment-Decoder

Description: 用VHDL语言在FPGA上实现将十进制bcd码转换成七段led显示码-FPGA using VHDL language to achieve will be converted to decimal bcd yards led seven segment display code
Platform: | Size: 1024 | Author: 吴金通 | Hits:

[Other] seven_seg_decoder

Description: ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment display. different LEDS need to be lighted for displaying no. -ITS A verilog HDL code for seven segment display .. on different FPGA there are seven segment displays available .. any number from 0 to 9 can be displayed on it .. using this decoder a BCD input is required .. that would be decoded to seven segment display. different LEDS need to be lighted for displaying no.
Platform: | Size: 1024 | Author: hassan | Hits:

[VHDL-FPGA-Verilog] BCD

Description: BCD码和二进制之间的转化，FPGA中的实现，内附原理及代码！-BCD conversion between binary code and, FPGA Realization of, containing principles and code!
Platform: | Size: 165888 | Author: rbj | Hits:

[VHDL-FPGA-Verilog] B_to_D

Description: 二进制转BCD码程序，可作为7段数码管显示的编解码程序，VHDL编写的FPGA工程。-BCD binary code change process, as 7 digital display codec process, VHDL FPGA project prepared.
Platform: | Size: 1009664 | Author: 程光 | Hits:

[VHDL-FPGA-Verilog] P1-Contador-BCD

Description: Practice 1 FPGA ITCH Xilinx
Platform: | Size: 919552 | Author: Rafaeleg | Hits:

[VHDL-FPGA-Verilog] DECODER7

Description: 基于FPGA的BCD/七段译码器的设计，QuartusII编译通过，采用VHDL语言编写。-Based on FPGA BCD/these seven decoder design, QuartusII compile, USES the VHDL language.
Platform: | Size: 286720 | Author: 左云华 | Hits:

[MPI] BCD_ok-BCD

Description: Verilog 4位计时器,可以在CPLD开发板上成功运行-Verilog CPLD FPGA
Platform: | Size: 214016 | Author: 猎狐 | Hits:

[VHDL-FPGA-Verilog] bcd2ftsegdec

Description: FPGA bcd 7 segments display example
Platform: | Size: 2048 | Author: 王俊霖 | Hits:

[VHDL-FPGA-Verilog] BCD-CODE

Description: 基于FPGA的二进制转BCD码程序，非常适合初级菜鸟学习使用入门程序，欢迎大家下载学习-FPGA binary code to BCD based procedures, very suitable for learning to use primary rookie entry procedures, are welcome to download the learning
Platform: | Size: 44032 | Author: zhang yang | Hits:

[Other] 至简设计法--篮球倒计时

Description: 篮球倒计时 工程说明 本项目包含2个按键和4位数码管显示，要求共同实现一个篮球24秒的倒计时，并具有暂停和重新计数复位的功能。 案例补充说明 与单片机等实现模式相比，FPGA倒计时系统大大简化，整体性能和可靠性得到提高。在篮球24秒倒计时的模块架构设计方面，只需要一级架构下的BCD译码模块、倒计时模块和数码管显示模块，即可实现24秒倒计时功能。(Basketball countdown Engineering description This project contains 2 buttons and 4 digital display, which requires a basketball countdown of 24 seconds, and has the function of pause and count reset. Case Supplement Compared with the implementation mode of MCU, the FPGA countdown system is greatly simplified, and the overall performance and reliability are improved. In basketball 24 seconds countdown module architecture design, only need a framework under the BCD decoding module, countdown module and digital display module, can achieve 24 seconds countdown function.)
Platform: | Size: 56320 | Author: 明德扬科教 | Hits:

[Other Embeded program] bcd

Description: FPGA实现3-8译码器用于实验测试，非常适合于初学者(FPGA implementation decoder)
Platform: | Size: 160768 | Author: 王一9 | Hits:

[VHDL-FPGA-Verilog] 串口电压表VHDL

Description: 使用 AD 转换器 TLV1570，将 0－2.5V 的电压转换成 10 位二进制结果，再将 10 位二进制结果转换成 4 位 BCD 码 （整数部分 1 位，小数部分 3 位），并通过 UART 串口将数据送上位机 （电脑）进制显示(Serial port voltmeter)
Platform: | Size: 4210688 | Author: LB明 | Hits:
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