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Description: 用EPM7032（CPLD）做的２路８位并行输入ＤＡＣ，带内部环型振荡器（不用外接时钟振荡源）。
Platform: |
Size: 2932 |
Author: 邵刚 |
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Description: (1) This pin may function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG
ports for in-system programming, this pin is not available as a user I/O pin.
(2) The user I/O pin count includes dedicated input pins and all I/O pins.-(1) This pin may function as either a JTAG po rt or a user I/O pin. If the device is configured t o use the JTAG ports for in-system programming. this pin is not available as a user I/O pin. (2) Th e user I/O pin count includes dedicated input pi ns and all I/O pins.
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Size: 29696 |
Author: 李国 |
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Description: 用EPM7032（CPLD）做的２路８位并行输入ＤＡＣ，带内部环型振荡器（不用外接时钟振荡源）。-With EPM7032 (CPLD) to do 2-way 8-bit parallel input DAC, with the internal ring oscillator (no external clock oscillation source).
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Size: 3072 |
Author: 邵刚 |
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Description: altera 公司的EPM7032和EPM7128的DATASHEET-altera s EPM7032 and EPM7128 of DATASHEET
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Size: 967680 |
Author: joseph |
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Description: CPLD学习，用VHDL,应用EPM7032,一个138，373和273的例程-CPLD study, using VHDL, application EPM7032, one of the routines 138,373, and 273
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Size: 100352 |
Author: YAN |
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Description: 本文介绍一种用Altera公司的可编程逻辑器件EPM7032，在MAX＋PlusⅡ开发环境下采用VHDL语言以及ByteBlaster在线可编程技术来实现自动交通控制系统的方法。该设计中采用的自顶向下的设计方法同样适用于复杂数字系统的设计。 -VHDL语言以及ByteBlaster在线可编程技术来实现自动交通控制系统的方法。该设计中采用的自顶向下的设计方法同样适用于复杂数字系统的设计。
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Size: 78848 |
Author: 望先生 |
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Description: ALTETRA EPM7032 ENCODE正反轉16位元輸出+14輸入+內碼-ALTETRA EPM7032 ENCODE
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Size: 64512 |
Author: 麻吉 |
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Description: 这是本人亲自造过的CPLD最小系统图纸，保证可以用，因为造出过实物的，可以找我问问题或者买样品，付材料钱和运费就可以了(This is the CPLD minimum system drawing I made by myself. It guarantees that it can be used, because it can ask me questions or buy samples, and pay for material and shipping cost.)
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Size: 21504 |
Author: 格兰芬多狮 |
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