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Description: Wavelets have widely been used in many signal and image processing applications. In this paper, a new
serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet
transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline
architecture to compress and decompress images. The real filter calculation over 4 · 4 window blocks is
done using a tree of carry save adders to ensure the high speed processing required for many applications.
The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis
reveals that the proposed architecture, implemented using current VLSI technologies, can process a
video stream in real time.-Wavelets have been widely used in many sign al and image processing applications. In this p aper. a new serial-parallel architecture for wavele t-based image compression is introduced. It is based on a 4-tap wavelet transform. which is realized using some FIFO memory module 's implementing a pixel-level pipeline archite cture to compress and decompress images. The're al filter calculation over 4 blocks window is done using a tree of carry save adders to ensure t he high speed processing required for many appl ications. The details of implementing both com pressor decompressor and sub-systems are give n. The primarily analysis reveals that the prop osed architecture, VLSI implemented using current technologies, can process a video stream in real time.
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Size: 2837459 |
Author: sdfafaf |
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Description: DSP中输入信号的生成过程。 conio.cpp实现X(n)信号，其中有两个频率分量的正弦信号（正弦计算由sinwn.cpp实现），频率可变，这里取140Hz和70Hz。 考虑了高斯白噪声，由gauss.cpp实现。 最后该信号共产生2000个点，最后的信号点存储于 “x.txt”文本中。-DSP input signal generation process. Conio.cpp achieve X (n) signal, in which there are two components of the frequency sinusoidal signals (sine calculation sinwn.cpp achieved), variable frequency, here and frequencies from 140Hz. Consider a Gaussian white noise from gauss.cpp achieve. Finally, the signal generated 2,000 points, the final point signal storage in the "x.txt" text.
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Size: 1662 |
Author: feide |
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Description: DSP编程常用函数 double uniform(double a,double b,long int* seed) double gauss(double mean,double sigma,long int *seed) double exponent(double beta,long int *seed) double laplace(double beta,long int* seed) double rayleigh(double sigma,long int *seed) double weibull(double a,double b,long int*seed) int bn(double p,long int*seed) int bin(int n,double p,long int*seed) int poisson(double lambda,long int *seed) void dft(double x[],double y[],double a[],double b[],int n,int sign) void fft(double x[],double y[],int n,int sign)-DSP programming functions commonly used double uniform (a double, double b, long int* seed) double Gauss (double mean, double sigma, long int* seed) double exponent (double beta, long int* seed) double Laplace (double beta,* long int seed) double Rayleigh (double sigma, long int* seed) double Weibull (a double, double b, long int* seed) int bn (double p, long int* seed) int bin (int n, p double, seed long int*) int poisson (double lambda, long int* seed) void dft index (double x [], double y [], [] a double, double b [], int n, int sign) void fft (double x [], double y [], int n, int sign)
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Size: 2048 |
Author: 山城棒棒儿军 |
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Description: DSP中输入信号的生成过程。 conio.cpp实现X(n)信号，其中有两个频率分量的正弦信号（正弦计算由sinwn.cpp实现），频率可变，这里取140Hz和70Hz。 考虑了高斯白噪声，由gauss.cpp实现。 最后该信号共产生2000个点，最后的信号点存储于 “x.txt”文本中。-DSP input signal generation process. Conio.cpp achieve X (n) signal, in which there are two components of the frequency sinusoidal signals (sine calculation sinwn.cpp achieved), variable frequency, here and frequencies from 140Hz. Consider a Gaussian white noise from gauss.cpp achieve. Finally, the signal generated 2,000 points, the final point signal storage in the "x.txt" text.
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Size: 1024 |
Author: feide |
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Description: TI的DSP网络部分网络的接口测试的程序。通过闭环发送和接收。程序为TI编写，网络队列和堆栈的操作十分经典。-TI DSP network parts of the network interface test procedures. Through closed-loop send and receive. TI procedures for the preparation, network stack and queue operation classical.
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Size: 487424 |
Author: 靳朝 |
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Description: DES,MD5,ZLIB算法源代码
文件列表：
Adler32.cpp
ArithDLL.cpp
ArithDLL.def
ArithDLL.dll
ArithDLL.dsp
ArithDLL.dsw
ArithDLL.h
ArithDLL.lib
ArithDLL.ncb
ArithDLL.opt
ArithDLL.plg
Arithzxz.h
Arithzxz.h.BAK
Compress.cpp
CRC.cpp
Deflate.cpp
Deflate.h
Des.cpp
Des.h
Infblock.cpp
Infblock.h
Infcodes.cpp
Infcodes.h
Inffast.cpp
Inffast.h
Inffixed.h
Inflate.cpp
Inftrees.cpp
Inftrees.h
Infutil.cpp
Infutil.h
md5.cpp
md5.h
ReadMe.txt
StdAfx.cpp
StdAfx.h
String.cpp
Trees.cpp
Zlib.h
Zutil.cpp
Zutil.h-DES, MD5, ZLIB algorithm source code files list : Adler32.cpp ArithDLL.cpp ArithDLL.def Arith DLL.dll ArithDLL.dsp ArithDLL.dsw ArithDLL. h ArithDLL.lib Ari ArithDLL.ncb ArithDLL.opt thDLL.plg Arithzxz.h Arithzxz.h.BAK Compres s.cpp CRC.cpp Deflate.cpp Deflate.h Des.cpp D es.h Infblock.cpp In Infblock.h Infcodes.cpp fcodes.h Inffast.cpp In Inffast.h Inffixed.h flate.cpp Inftrees.cpp Inftrees.h Infutil.c pp Infutil.h md5.cpp StdAfx md5.h ReadMe.txt file. cpp StdAfx.h String.cpp Trees.cpp Zlib.h Zuti l.cpp Zutil.h
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Size: 138240 |
Author: water1974 |
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Description: 1、（1）32bit乘法的指令解释
（2）volume1的load.asm基础上实现一个
16bit数组的乘法累加的函数，并进行 -o2 / -o3 / 手工优化
2、c环境
C调用汇编函数，汇编函数调用c函数
addarr3(int * arr1, int * arr2, int * arr3, int * arr4, n)
//汇编函数，3个数组的对应位置相加，结果放在arr4[n]中，
汇编函数调用C的子函数，它把arr1和arr2相加放到arr3[n]中；
addarr2(int * arr1, int * arr2, int * arr3, n)-1, (1) 32bit multiplication instructions explained (2) the load.asm volume1 on the basis of a a 16bit multiplication cumulative array of functions, and-o2 /-o3/2 manual optimization, c environment compilation called C function, the compilation function call c function addarr3 (int* arr1. int* arr2, arr3 int*, int* arr4, n)// compilation function, 3 arrays corresponding location together, the results on arr4 [n], the compilation of the C function call function, arr1 put it together and put arr2 arr3 [n]; addarr2 (int* arr1, int* arr2, int* arr3, n)
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Size: 27648 |
Author: 郭春吉 |
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Description: Wavelets have widely been used in many signal and image processing applications. In this paper, a new
serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet
transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline
architecture to compress and decompress images. The real filter calculation over 4 · 4 window blocks is
done using a tree of carry save adders to ensure the high speed processing required for many applications.
The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis
reveals that the proposed architecture, implemented using current VLSI technologies, can process a
video stream in real time.-Wavelets have been widely used in many sign al and image processing applications. In this p aper. a new serial-parallel architecture for wavele t-based image compression is introduced. It is based on a 4-tap wavelet transform. which is realized using some FIFO memory module 's implementing a pixel-level pipeline archite cture to compress and decompress images. The're al filter calculation over 4 blocks window is done using a tree of carry save adders to ensure t he high speed processing required for many appl ications. The details of implementing both com pressor decompressor and sub-systems are give n. The primarily analysis reveals that the prop osed architecture, VLSI implemented using current technologies, can process a video stream in real time.
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Size: 2837504 |
Author: sdfafaf |
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Description: 设信号 ，用 对x(t)采样得x(n)，是否会发生频谱混叠？现利用FFT分析其频谱。
1．编程绘制该信号的波形。
2．若令N=16，编程对x(n)做FFT运算，并绘制其幅频特性曲线。
3．令N=1024，编程对x(n)做FFT运算，并绘制其幅频特性曲线。
4．分析2、3的运算结果。
设计调试报告要求：
1．工作原理简述；
2．设计思路；
3．难点及解决方法；
4．设计、调试结果及分析；
5．程序文本及操作步骤。-based signal used to x (t) in the sample x (n), whether there will be a spectrum aliasing? FFT analysis is the use of their spectrum. 1. Programming mapping of the signal waveform. 2. If so N = 16, the programming of x (n) do FFT, and the mapping of its amplitude-frequency characteristic curve. 3. Order N = 1024, the programming of x (n) do FFT, and the mapping of its amplitude-frequency characteristic curve. 4. Analysis of two, three computational results. Design debugging reporting requirements : 1. Principle outlined; 2. Design; 3. Difficulties and solutions; 4. Design, debugging and analysis of results; 5. Text and operating procedures steps.
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Size: 49152 |
Author: 魏臻 |
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Description: 开发TIC6000DSP经典重要资料,NDK(Network Development Kit) for TI C6000 DSP,本人费尽心血才搞到的,是开发DSP网络通讯的基础.-development TIC6000DSP classical important information NDK (Network Development Kit) for TI C6000 DSP, I only made a painstaking, and the development of DSP-based communications network.
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Size: 539648 |
Author: John NI |
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Description: 本例载波频率为20KHz，或载波周期为50μs。DSP晶振10MHz，内部4倍频，时钟频率为40MHz，计数周期为25ns。假设调制波频率由外部输入（1～50Hz），并转换成合适的格式（本例为Q4格式）。调制系数M为0～0.9。死区时间1.6μs。最小删除脉宽3μs。
主程序的工作是根据输入的调制波频率计算N、2N和M值。
-Example for the carrier frequency 20KHz, or carrier period is 50μs. DSP crystal 10MHz, internal 4 multiplier, the clock frequency of 40MHz, counting cycle 25ns. Assuming wave frequency modulation by external input (1 ~ 50Hz), and converted into an appropriate format (in this case for Q4 format). Modulation coefficient M is 0 ~ 0.9. Dead time 1.6μs. Delete the smallest pulse width 3μs. The work of the main program is based on input frequency modulation wave calculation of N, 2N and M values.
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Size: 15360 |
Author: liuhx |
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Description: TI公司的NSP，ndk开发必备 dsp网络实现-TI
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Size: 2302976 |
Author: liuyi |
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Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型
化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了
三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
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Size: 546816 |
Author: John |
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Description: DFT 计算
实验步骤：
主界面下进入实验九的“DFT计算”的子实验。
输入取样点数，即有限长序列 x(n) 的长度。
输入信号表达式，或直接输入离散序列。
鼠标单击确定按钮，显示原序列及 DFT 系数的幅度、相位。-DFT calculation of the experimental steps: the main interface into the experimental Kau " DFT calculation of" sub-experiment. Enter the sampling points, that is, finite sequences x (n) length. Expression of the input signal, or directly onto a discrete sequence. Mouse click OK button to display the original sequence and the magnitude of DFT coefficients, phase.
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Size: 49152 |
Author: 高荣 |
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Description: MC9S12单片机 IIC总线发送和接受1字节和N字节数据-IIC-bus single-chip MC9S12 send and receive 1 byte of data bytes and N
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Size: 2048 |
Author: xuechi |
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Description: 针对电梯数据采集数目较多和数据处理复杂等特点,提出了基于数字信号处理器(DSP)和现场可编程门阵列(FPGA)的电梯智能数据采集系统。在介绍了系统整体结构及各组成子模块后,给出了模块与器件之间硬件接口设计思路和架构,描述了整个系统的软件框架,设计了DSP、AD采样、网络通信和抗干扰等程序。整个系统在工程应用中易于实现,具有很好的推广价值-n accordance with the characteristic of elevator for the large number of data acquisition and handling data complicated, an el- evator data acquisition system based on digital signal processor (DSP) and field programmable gate array (FPGA) is given. After system structure and modules are introduced, the design of interfaces of the hardware and framework between modules and devices are provided, the software design used in the system is described, the DSP, AD sampling, network communication
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Size: 179200 |
Author: 将建 |
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Description: 利用TS201超高性能的计算处理能力以及FPGA支持的高速接口交换能力,实现了一种对算法的适应性强、结构扩展方便的通用信号处理板,设计了一种基于该通用信号处理板的米波雷达阵列信号处理系统,并以幅相校正、自适应旁瓣相消的算法实现为例,详细介绍了该阵列信号处理系统算法的实现方法。该系统运行稳定可靠,达到了系统的设计要求。-n this paper,multiple DSPs are adopted to design the array signal processing system.By utilizing the high processing ability of the TS201 and the high-speed data exchange ability supported by FPGA,a general array signal processing system with strong adaptability and easy-expansion ability is fulfilled for radar signal processing.Implementation of the algorithm,such as ASLC and calibration of magnitude and phase,is described in detail.The whole system works well,and meets the requirement of the system...
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Size: 429056 |
Author: 将建 |
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Description: 印度GURUNANAK ENGINEERING COLLEGE数字信号处理实验室的DSP+c+Matlab联合编程手册-DIGITAL SIGNAL PROCESSING LAB (IV-I SEM)
INDEX
1. Architecture of DSP chips-TMS 320C 6713 DSP Processor
2. Linear convolution
3. Circular convolution
4. FIR Filter (LP/HP) Using Windowing technique
a. Rectangular window
b. Triangular window
c. Kaiser window
5. IIR Filter(LP/HP) on DSP processors
6. N-point FFT algorithm
7. Power Spectral Density of a sinusoidal signals
8. FFT of 1-D signal plot
9. MATLAB program to generate sum of sinusoidal signals
10. MATLAB program to find frequency response of analog
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Size: 1582080 |
Author: wangjin |
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Description: Tutorial of filter: design a lowpass FIR filter of cutoff requency 0.3*pi. Plot the impulse responses h(n) and magnitude responses of the designed filters
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Size: 138240 |
Author: Hau Nguyen |
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Description: 为了产生一个PWM信号，DSP的定时器定时周期应该和PWM的周期相等。另外需要对DSP的EVA/EVB模块中的比较单元的比较寄存器设定数值，这样该数值一直与定时器的计数器值相比较，按照一定的比较方式，PWM即产生跳变。通过此种方式，DSP的PWM管脚就会产生一个宽度与比较寄存器数值成比例的脉冲信号。在定时器重复定时的过程中就产生了PWM信号。
使用DSP比较单元产生PWM波形不需要硬件连接图，只需对DPS的相关寄存器进行配置就可以在输出端得到相应的PWM波形，其具体操作过程如下：
1设置比较方式控制寄存器ACTRx
2如有必要，使能死区功能，配置死区控制寄存器DBTCONx
3对比较寄存器CMPRx赋值
4设置定时器寄存器T1CON（T3CON）并启动定时
5通过更新CMPRx的数值改变PWM占空比的大小
-n order to generate a PWM signal, DSP timer timer and PWM cycle period should be equal. In addition the need for DSP s EVA/EVB module compare unit compare register setting values, so that the value and the timer counter value has been compared by some comparisons, PWM that generate transition. In this way, DSP s PWM pin will generate a value of compare register width is proportional to the pulse signal. Repeated regularly in the course of the timer to generate a PWM signal.
Compared using the DSP hardware unit generates PWM waveforms do not need connection diagram, only the relevant registers of the DPS can be configured to obtain the corresponding PWM output waveform, the specific operation is as follows:
Comparison of mode control register 1 set ACTRx
2 If necessary, enable the dead zone function, the configuration control register DBTCONx dead
3 on the comparison registers CMPRx assignment
4 Set the timer register T1CON (T3CON) and start the timer
5, the value changes by upd
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Size: 4096 |
Author: zhangchao |
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