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[VHDL-FPGA-Verilog] des-verilog

Description: des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language
Platform: | Size: 67584 | Author: 杨云丰 | Hits:

[Crack Hack] des

Description: 用VERILOG语言实现的数据加密标准代码,在QUARTUS5.1上仿真过-Using Verilog language code of the Data Encryption Standard, in the simulation had QUARTUS5.1
Platform: | Size: 1436672 | Author: zhang feng | Hits:

[Crack Hack] DES_verilog

Description: this DES made by verilog
Platform: | Size: 15360 | Author: Shawn | Hits:

[Crack Hack] DES_Verilog

Description: 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test report, which not only have a simple Notes program [is mainly directed against the waveform simulation], I write is the main control part key generation is partly based on the next version of the original Yasuhiro procedures. The program can also be encrypted can be decrypted, CycloneII optional devices which can run more than 100Mhz.
Platform: | Size: 296960 | Author: jesse | Hits:

[Crack Hack] DES

Description: DES算法的verilog实现，实现了硬件IC对DES的构架，可以直接应用在系统当中。-DES algorithm Verilog realized, the realization of the hardware IC framework of DES, can be directly used in the system.
Platform: | Size: 10240 | Author: 金鑫 | Hits:

[VHDL-FPGA-Verilog] DES

Description: This is verilog source code for DES(Data Encryption standard) which is used in network security.
Platform: | Size: 20480 | Author: Krupesh | Hits:

[Crack Hack] aes_thesis_v1.0

Description: AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
Platform: | Size: 386048 | Author: 蕭嵎之 | Hits:

[VHDL-FPGA-Verilog] DES

Description: 在ISE平台上，利用Verilog编程实现数据的DES加密-In the ISE platform, using Verilog programming DES data encryption
Platform: | Size: 661504 | Author: ldh | Hits:

[Crack Hack] DES_Encrypt_Decrypt_Verilog

Description: DES加密算法的Verilog HDL实现，带模式选择端口，可以实现加密和解密，已经modelsim仿真通过。-Des En/Decrypt,Verilog HDL code
Platform: | Size: 8192 | Author: Amazing_Eric | Hits:

[Crack Hack] topic

Description: DES加密算法的VHDL和VERILOG源程序- Xilinx开源共享61EDA代码工厂-DES encryption algorithm of VHDL and VERILOG source code- Xilinx factory open source code sharing 61EDA
Platform: | Size: 274432 | Author: renkaiqiang | Hits:

[VHDL-FPGA-Verilog] des

Description: des解密加密的verilog源代码其中包含有测试源代码，仿真结果图-verilog des decrypt encrypted source code which includes testing the source code, Simulation results
Platform: | Size: 343040 | Author: cong | Hits:

[VHDL-FPGA-Verilog] limited_des

Description: this DES encryption and decryption code in verilog-this is DES encryption and decryption code in verilog
Platform: | Size: 961536 | Author: neha | Hits:

[VHDL-FPGA-Verilog] My_DES3

Description: a triple-DES (Data Encryption Standard) hardware description in verilog-HDL with testbench
Platform: | Size: 861184 | Author: Farzad | Hits:

[VHDL-FPGA-Verilog] Encrypt_Decrypt(DES)_Verilog

Description: Encrypt and decrypt DES algorithm in verilog
Platform: | Size: 8192 | Author: hr | Hits:

[VHDL-FPGA-Verilog] DES_Triple-DES-IP-Cores

Description: Triple DES 密码算法。 利用Xillinx公司的Virtex-II芯片测试了。正常动作。-Triple DES core implementation in verilog. It takes three standard 56 bit keys and 64 bits of data as input and generates a 64 bit encrypted/decrypted result.
Platform: | Size: 70656 | Author: 金铁男 | Hits:

[Other] des_latest.tar

Description: 利用verilog实现的DES和3DES两种加密算法，其中每个算法又利用了两种实现方式，分别是面积优先和性能优先-Both use DES and 3DES encryption algorithms verilog implementation, which took advantage of each algorithm implemented in two ways, which are the priority and performance priority area
Platform: | Size: 41984 | Author: 程鹏 | Hits:

[Crack Hack] DES_orginal_core

Description: this a DES encryption code in verilog-this is a DES encryption code in verilog
Platform: | Size: 22528 | Author: tahmoures | Hits:

[Crack Hack] des

Description: DES in verilog codes
Platform: | Size: 11264 | Author: Ni Ni | Hits:

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