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[VHDL-FPGA-Verilog] Audio_DAC_FIFO

Description: altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以用一条语句实现，音频解码的输出。-altera
Platform: | Size: 15360 | Author: 朱峰 | Hits:

[Other] Cyclone_II_FPGA_sch

Description: altera 飓风二代开发板的原理图，pdf格式 -altera hurricane of the second generation development board schematics, pdf format
Platform: | Size: 236544 | Author: dansen | Hits:

[Software Engineering] Cyclone_II_EP2C35_DSP

Description: fpga开发板原理图，参考使用，请下载研究-FPGA development board schematics, use and reference, please download study
Platform: | Size: 1269760 | Author: ltlt | Hits:

[VHDL-FPGA-Verilog] rel_08_done

Description: 修改自OpenCores的黑白棋游戏代码。采用VGA输出显示，PS2键盘（W、A、S、D、回车）输入控制，实现AI，LED灯指示是否游戏结束，VGA显示频率25MHz，系统频率50MHz，经过Cyclone IV芯片EP4CE115F29C7N的板级调试，实现全部功能，文件夹下有rtl源代码，管脚定义pin文件，和可以直接进行JTAG烧写和E2PROM烧写的pof和sof文件，-Modified from OpenCores Othello game code. Using the VGA output display, PS2 keyboard (W, A, S, D, Enter) input control to achieve AI, LED lights indicate whether the game is over, VGA display frequency of 25MHz, the system frequency of 50MHz, after Cyclone IV chip, board-level debugging EP4CE115F29C7N to achieve full functionality, folder there rtl source code, pin definition of pin file, and can be programmed and the JTAG programming of pof and E2PROM sof file,
Platform: | Size: 252928 | Author: 诗律 | Hits:

[VHDL-FPGA-Verilog] dwn_sampler

Description: Multirate digital signal processing system which includes sampling rate conversion. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is downsampler FPGA implementation of the same is presented. The FPGA synthesis results are verified and report is presented. In order to build down sampler consisting of D F/F and clock generator, are downloaded on cyclone-II FPGA-Multirate digital signal processing system which includes sampling rate conversion. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is downsampler FPGA implementation of the same is presented. The FPGA synthesis results are verified and report is presented. In order to build down sampler consisting of D F/F and clock generator, are downloaded on cyclone-II FPGA
Platform: | Size: 2048 | Author: Mohan Reddy | Hits:

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