Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - CYCLONE EP2C5

Search list

[Other resource] EP2C5_SCH

Description: Cyclone II EP2C5实验开发板原理图PDF文件-Cyclone II development board EP2C5 experimental diagram PDF files
Platform: | Size: 444987 | Author: 高 | Hits:

[Software Engineering] EP2C5_SCH

Description: Cyclone II EP2C5实验开发板原理图PDF文件-Cyclone II development board EP2C5 experimental diagram PDF files
Platform: | Size: 444416 | Author: 高 | Hits:

[VHDL-FPGA-Verilog] EP2C5Q208

Description: 以cyclone系列的EP2C5Q208为核心的实验板程序.包括流水灯,I2C存储器.SPI存储器,数码管,串口,LCD等-Cyclone in series as the core EP2C5Q208 experimental procedure. Including water lights, I2C memory. SPI memory, digital control, serial port, LCD, etc.
Platform: | Size: 2980864 | Author: sarah | Hits:

[VHDL-FPGA-Verilog] ep2c5-pininformation

Description:
Platform: | Size: 86016 | Author: sun huaiming | Hits:

[SCM] EP2C5

Description: Altera FPGA Cyclone II EP2C5 最小系统 开发板-the minimum system of Altera FPGA EP2C5 and or EP2C8
Platform: | Size: 588800 | Author: 长官林 | Hits:

[VHDL-FPGA-Verilog] EP2C5

Description: Altera提供的CycloneII的orCAD封装库-Altera provided CycloneII the OrCAD library package
Platform: | Size: 8192 | Author: tony.chen | Hits:

[VHDL-FPGA-Verilog] EP2C5_SCH

Description:
Platform: | Size: 444416 | Author: qibinchuan | Hits:

[Software Engineering] CycloneEP2C5

Description: 主流FPGA Cyclone EP2C5 原理图设计 -Cyclone EP2C5
Platform: | Size: 444416 | Author: 王维 | Hits:

[VHDL-FPGA-Verilog] weitb

Description: 在数字通信中，通常直接从接收到的数字信号中提取位同步信号，这种直接法按其提取同步信号的方式，大致可分为滤波法和锁相法。锁相法是指利用锁相环来提取位同步信号的方法，本设计方案就是基于锁相环的位同步提取方法，能够比较快速地提取位同步时钟，并且设计简单，方便修改参数。采用Quartus II设计软件对系统进行了仿真试验，并用Altera的Cyclone II系列FPGA芯片Ep2c5予以实现。-In digital communication, usually from receiving directly in digital signal extracted a synchronized signal, the direct method according to the extraction synchronized signal way, can be roughly divided into filtering method and phase lock method. Phase lock method is using of phase locked loop to extract a synchronized signal method, the design scheme is based on phase locked loop of a synchronous extraction method and can be quickly extract a synchronous clock, and design simple, convenient modification parameter. The Quartus II design software of the system, and the simulation test Altera Cyclone II FPGA chip to achieve Ep2c5 series.
Platform: | Size: 595968 | Author: dandan | Hits:

[Software Engineering] ep2c5

Description: altera 公司提供的 Pin Information for EP2C5-Pin Information for the Cyclone II EP2C5 Device
Platform: | Size: 86016 | Author: sean | Hits:

[VHDL-FPGA-Verilog] DM5_VGA_img_C5H

Description: 基于FPGA的VGA输入采集工程示例，是基于ALTERA公司的CycloneⅡ的EP2C5芯片，具有一定的参考价值。-VGA input sample collection project based FPGA is based on the company s CycloneⅡ of EP2C5 ALTERA chip, has a certain reference value.
Platform: | Size: 88064 | Author: 安庆隆 | Hits:

[VHDL-FPGA-Verilog] DDS_Core_Norml_ADDA_C5H

Description: 基于FPGA的DDS内核的信号采集和输出，是基于ALTERA公司的CycloneⅡ的EP2C5芯片，是一个很好的参考示例。-DDS core FPGA-based signal acquisition and output is based on the company s CycloneⅡ of EP2C5 ALTERA chip, is a good reference example.
Platform: | Size: 477184 | Author: 安庆隆 | Hits:

CodeBus www.codebus.net