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[Post-TeleCom sofeware systemscrc32

Description: --循环冗余计算的并行实现代码 --初始值是全0或全1都可以-Cyclic redundancy code realize parallel computing the initial value is 0 or 1 whole can be
Platform: | Size: 1024 | Author: luvicee | Hits:

[VHDL-FPGA-Verilogcrc

Description: 可以直接用于工程应用的crc校验VHDL编码 里面有详细的规格书-Can be directly used for engineering applications of CRC checksum inside VHDL code has detailed specifications
Platform: | Size: 90112 | Author: 毋杰 | Hits:

[Crack HackCrc_Parallel

Description: CCITT Parallel CRC 16-bit
Platform: | Size: 1024 | Author: timngo | Hits:

[Communicationconv.vhd

Description: 卷积编码的VHDL代码,公司内部资料,不是个人随便编写的-VHDL code of convolutional encoding
Platform: | Size: 6144 | Author: 魏强 | Hits:

[Communication-Mobilecrc.vhd

Description:
Platform: | Size: 5120 | Author: 魏强 | Hits:

[Othercrc_peripheral

Description: -- crc.vhd -- Used for calculation of CRC16-CCITT -- Intended use is as custom peripheral for Nios processor -- When address is logic 0 => -- Internal CRC register is initialised with write_data value -- When address is logic 1 => -- CRC calulation is updated based on input word on write_data -- CRC result is obtained by reading any address
Platform: | Size: 1024 | Author: Jan Petak | Hits:

[VHDL-FPGA-VerilogCRC.vhd

Description: CRC 8bit for bus monitor
Platform: | Size: 1024 | Author: 郭涛 | Hits:

[Algorithm16-bit-Serial-CRC-CCITT-Generator.vhd.tar

Description: 16-bit Serial CRC-CCITT Generator
Platform: | Size: 1024 | Author: FranxCuckoo | Hits:

[AlgorithmPCK_CRC16_D32.vhd.tar

Description: synthesizable CRC function WITH polynomial: (0 2 15 16), data width: 32
Platform: | Size: 1024 | Author: FranxCuckoo | Hits:

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