Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - AES in verilog

Search list

[Crack Hack] aes_core

Description: Verilog实现AES加密算法 密码模块作为安全保密系统的重要组成部分，其核心任务就是加密数据。分组密码算法AES以其高效率、低开销、实现简单等特点目前被广泛应用于密码模块的研制中。密码模块一般被设计成外接在主机串口或并口的一个硬件设备或是一块插卡，具有速度快，低时延的特点。而从整体发展趋势来看，嵌入式密码模块由于灵活，适用于多种用户终端、通信设备和武器平台，将会得到更加广泛的应用-AES encryption algorithm realize Verilog module password security system as an important part of its core mission is to encrypt the data. AES block cipher algorithm for its high efficiency, low overhead, simple features such as the current password is widely used in research and development modules. Password modules are generally designed to host external serial or parallel port of a hardware device or a card with a high speed, low latency characteristics. From the overall development trend, the embedded code module as a result of flexible and applicable to many user terminals, communications equipment and weapons platforms, will be more widely applied
Platform: | Size: 79872 | Author: yuansuchun | Hits:

[VHDL-FPGA-Verilog] aes_core.tar

Description: AES的Verilog实现,用于加密的算法硬件实现!-AES realize the Verilog for hardware implementation of encryption algorithms!
Platform: | Size: 69632 | Author: 刘志刚 | Hits:

[VHDL-FPGA-Verilog] AES_RTL

Description: 使用Verilog HDL 實現AES硬體加解密-Realize the use of Verilog HDL hardware AES encryption and decryption
Platform: | Size: 15360 | Author: 林夢魔 | Hits:

[source in ebook] 63535312DCTofJPEG

Description: 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition
Platform: | Size: 2048 | Author: jiang | Hits:

[Crack Hack] systemcaes_latest.tar

Description: 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
Platform: | Size: 83968 | Author: lxc | Hits:

[Crack Hack] aes_thesis_v1.0

Description: AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
Platform: | Size: 386048 | Author: 蕭嵎之 | Hits:

[Crack Hack] AES_verilog

Description: AES 128bit数据,128bit密钥加解密的verilog语言实现-AES 128bit data, 128bit key encryption and decryption of the verilog language implementation
Platform: | Size: 79872 | Author: 刘蕊丽 | Hits:

[VHDL-FPGA-Verilog] aescore

Description: 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
Platform: | Size: 195584 | Author: 李华 | Hits:

[Crack Hack] aes

Description: 其程序是用xilinx环境下编写的，风格是Verilog，请大家提意见。-The program is written using xilinx environment, style Verilog, please comments.
Platform: | Size: 3072 | Author: 郝志刚 | Hits:

[Crack Hack] aes_crypto_core_latest.tar

Description: AES加密算法的Verilog实现，不包括测试文件-Verilog realization of AES encryption algorithm, not including test file
Platform: | Size: 1927168 | Author: sunyun | Hits:

[VHDL-FPGA-Verilog] sbox

Description: verilog code for s-box generation for AES algorith
Platform: | Size: 1024 | Author: clock | Hits:

[VHDL-FPGA-Verilog] aes_pipe_latest.tar

Description: implementation of AES encryption algorithm in vhdl/verilog
Platform: | Size: 188416 | Author: cooldude | Hits:

[VHDL-FPGA-Verilog] AESverilog

Description: AES加密算法的Verilog语言实现，通过编译-AES encryption algorithm in Verilog Implementation
Platform: | Size: 88064 | Author: 杨进 | Hits:

[VHDL-FPGA-Verilog] AES256-XILINX10.1

Description: 用XILINX公司提供的NetFPGA板卡并结合软件Xilinx10.1进行系统设计，采用硬件描述语言Verilog实现了 AES-256加密算法。-Provided by XILINX board combined with software Xilinx10.1 NetFPGA system design, using Verilog hardware description language implementation of the AES-256 encryption algorithm.
Platform: | Size: 5120 | Author: yuanying | Hits:

[CA auth] aes-module

Description: its a aes source code in verilog
Platform: | Size: 11264 | Author: p | Hits:

[Crack Hack] AES-based-on-FPGA-jiami

Description: 该模块是基于FPGA的AES加密算法实现的Verilog代码，包含一个顶层文件和两个调用模块，最高误差在15ns-This module is the AES encryption algorithm FPGA based on the Verilog code, contains a top-level files and two call module, the maximum error in 15ns
Platform: | Size: 14939136 | Author: 庄德坤 | Hits:

[Crack Hack] FPGA-IMPLEMENTATION-OF-AN-AES-PROCESSOR

Description: Advanced Encryption Standard(AES) implementing in a faster and secured way is expected. AES can be implemented in software/hardware. In hardware implementation ASIC solution requires high cost and much design time while FPGA based implementation offers lower cost, quicker and more customizable solution. This paper represents implementing AES in FPGA with minimum latency and speedy throughput where Verilog HDL is used to simulate the operations.
Platform: | Size: 218112 | Author: arif | Hits:

[VHDL-FPGA-Verilog] aes

Description: contains AES doc with code in Verilog
Platform: | Size: 961536 | Author: sravs | Hits:

[Crack Hack] aes_thesis_v1.0

Description: aes code in verilog vhdl language which is very useful.
Platform: | Size: 385024 | Author: sur22 | Hits:

[Crack Hack] aes

Description: AES in verilog codes
Platform: | Size: 28672 | Author: Ni Ni | Hits:
« 12 »

CodeBus www.codebus.net