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[GIS programregister

Description: 32×32的寄存器堆,它有32个32位的寄存器、两个读端口和一个写端口。该寄存器堆由3个层次共5个模块构成,最低层次的模块是D触发器,中间层次的模块包括32位寄存器、5位地址译码器、32选1多路选通器,顶层模块是寄存器堆模块。设计采用行为建模和结构建模相结合的方法,先用行为建模方法建立低层模块,然后再用结构建模方法搭建高层模块。-32 × 32 of the register file, it has 32 32-bit registers, two read ports and one write port. The register file by the three levels of a total of five modules, the lowest level module is the D flip-flop, middle-level module including 32-bit register, address decoder 5, 32 election more than one way strobe, and top-level module is Register File module. Design using behavioral modeling and structural modeling method of combining the first act of modeling methods used to establish low-level modules, then the structural modeling method to build high-level module.
Platform: | Size: 4096 | Author: | Hits:

[MacOS developREG32

Description: 32位寄存器的VHDL的原代码下载,COOLCOOLCOOL-32-bit register of the original VHDL code download, COOLCOOLCOOL
Platform: | Size: 3072 | Author: LIU | Hits:

[VHDL-FPGA-VerilogOPERATION_UNIT

Description: 本程序为加密芯片内部加密运算单元部分,包括32位减法器、移位寄存器、加/减法器、寄存器等,对密码芯片运算部分设计具有一定指导意义-The procedure for encryption chip unit internal encryption algorithms, including 32-bit subtraction, and shift register, add/subtraction, and register and so on password-chip design has a certain computing guide
Platform: | Size: 2048 | Author: zhaohongliang | Hits:

[VHDL-FPGA-Verilogregister

Description: it is source code of 32 bit register and testbench for tht register written in verilog.
Platform: | Size: 13312 | Author: bhaskar | Hits:

[Otherram

Description: 代码实现了一个由32位寄存器组成的寄存器组,并有多个控制输入和两个输出,方便使用。-The code implements a 32-bit register consisting of registers, and there are multiple control inputs and two outputs, easy to use.
Platform: | Size: 10240 | Author: Pang scotto | Hits:

[Windows DevelopALU_32

Description: 32 bit ALU design,LU Operations: This input specifies the ALU operation to be used during the acquisition process. The ALU operations are divided into logical operations and two classes of arithmetic operations. The two classes of arithmetic operations vary in how the CARRYIN register on the frame grabber card is set. A list of the 48 operations is given below:
Platform: | Size: 1024 | Author: madhawa | Hits:

[OtherMANIK

Description: MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instructions for code density • Von Neumann Architecture (Data and Instruction in the same address space). • Sixteen, 32 bit General Purpose Registers. • Four USER defined instructions (with Register File Write back capability).-MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instructions for code density • Von Neumann Architecture (Data and Instruction in the same address space). • Sixteen, 32 bit General Purpose Registers. • Four USER defined instructions (with Register File Write back capability).
Platform: | Size: 3395584 | Author: hfayed | Hits:

[Windows Developihoijge

Description: 掌握用Verilog HDL语言或VHDL语言设计一个由32个寄存器组成的字长为32位的寄 存器组。-Master the use of Verilog HDL or VHDL language design language a register composed of 32 32-bit word length for the device hosting group.
Platform: | Size: 855040 | Author: 陈淼 | Hits:

[VHDL-FPGA-Verilog32registergroup

Description: VHDL MIPS 32位寄存器组的设计-VHDL MIPS 32-bit register set design
Platform: | Size: 2690048 | Author: 逆天之刃 | Hits:

[Embeded-SCM DevelopARM

Description: ARM32位寄存器的设计,针对于32位寄存器的用VHDL语言编写的代码-ARM32-bit register, designed for 32-bit registers in the language with code written in VHDL
Platform: | Size: 1257472 | Author: 夏晨希 | Hits:

[VHDL-FPGA-VerilogARM32registergroup

Description: VHDL ARM 32位寄存器组的设计,基于Quartus II平台-VHDL ARM 32-bit register set design, based on the platform of Quartus II
Platform: | Size: 3068928 | Author: 逆天之刃 | Hits:

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