Search - 32 adder

[WEB Code] ripple-lookahead-carryselect-adder

Description: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL - sequence
Platform: | Size: 15972 | Author: 李成 | Hits:

[Other resource] Add64

Description: arm 上的64位加法，将32位加法扩展到64位，同理很容易扩大到128位-arm of the 64 Adder, 32 Adder expanded to 64, empathy can be easily expanded to 128
Platform: | Size: 12970 | Author: ricky | Hits:

[Streaming Mpeg4] sadct

Description: adi 汇编写的2维FDCT程序,分成两个1D-DCT,每个1D-DCT 使用12次乘法和32次加法-Sa'adi compilation of the two-dimensional writing FDCT procedures, divided into two 1D - DCT. Each one D-12 DCT use multiplication and 32 Adder
Platform: | Size: 38531 | Author: tohope | Hits:

[Documents] ripple-lookahead-carryselect-adder

Description: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL- sequence
Platform: | Size: 15360 | Author: 李成 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Add64

Description: arm 上的64位加法，将32位加法扩展到64位，同理很容易扩大到128位-arm of the 64 Adder, 32 Adder expanded to 64, empathy can be easily expanded to 128
Platform: | Size: 17408 | Author: ricky | Hits:

[Streaming Mpeg4] sadct

Description: adi 汇编写的2维FDCT程序,分成两个1D-DCT,每个1D-DCT 使用12次乘法和32次加法-Sa'adi compilation of the two-dimensional writing FDCT procedures, divided into two 1D- DCT. Each one D-12 DCT use multiplication and 32 Adder
Platform: | Size: 37888 | Author: tohope | Hits:

[MPI] source

Description: MIPS处理器VHDL代码，实现加法，减法乘除等运算，可综合，-MIPS processor VHDL code, realize adder, subtraction multiplication and division and other operations can be integrated,
Platform: | Size: 6144 | Author: 陈丰 | Hits:

[VHDL-FPGA-Verilog] 32addjiafaqi

Description: 32位加法器组成原理课程设计，串行进位完成，希望对大家有帮助-32-bit adder composed of the principle of curriculum design, the serial binary completed, we hope to help
Platform: | Size: 36864 | Author: 常鹏程 | Hits:

[MPI] add_16_bcd

Description: 此程序采用VHDL语言，完成在16位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的16位二进制加法器-This procedure using VHDL language, completed in 16-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 16 binary adder
Platform: | Size: 1024 | Author: 韩善华 | Hits:

[VHDL-FPGA-Verilog] add_32_bcd

Description: 此程序采用VHDL语言，完成在32位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的32位二进制加法器-This procedure using VHDL language, completed in 32-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 32 binary adder
Platform: | Size: 1024 | Author: 韩善华 | Hits:

[VHDL-FPGA-Verilog] add(FLP)

Description: 一个32位元的浮点数加法器，可将两IEEE 754格式内的值进行相加-A 32-bit floating-point adder can be both within the IEEE 754 format to add value
Platform: | Size: 10240 | Author: TTJ | Hits:

[VHDL-FPGA-Verilog] brentkung_32

Description: 32 bit brentkung adder tr-32 bit brentkung adder tree
Platform: | Size: 1024 | Author: suha | Hits:

[VHDL-FPGA-Verilog] koggestone_32

Description: koggee stone 32 bit adder
Platform: | Size: 1024 | Author: suha | Hits:

[VHDL-FPGA-Verilog] CSLA_32

Description: 32bit carry select adder
Platform: | Size: 1024 | Author: suha | Hits:

[VHDL-FPGA-Verilog] floating-point-adder1

Description: 基于VHDL语言的32位单精度的浮点加法器-floating point adder based on VHDL
Platform: | Size: 9216 | Author: Rosen | Hits:

[MiddleWare] ADDER

Description: 本设计是用32位的并行全加器的,可以实现浮点运算!-The design is a parallel 32-bit full adder, and floating-point operations can be achieved!
Platform: | Size: 278528 | Author: 王强 | Hits:

[Windows Develop] adder

Description: 8位cla，采用for结构，可以扩张成32位或者16位-8 cla, used for the structure, you can expand into a 32-bit or 16-bit
Platform: | Size: 36864 | Author: sigma | Hits:

[Other] adder

Description: 本设计是做了一个32位超前进位加法器，能够快速计算-This design is made of a 32-bit lookahead adder, to quickly calculate
Platform: | Size: 38912 | Author: zhaozimou | Hits:

[VHDL-FPGA-Verilog] Floating-Point-Adder

Description: 浮点数加法器IP核的vhd设计。浮点数加法运算是运输中使用最高的运算，结合vhdl和EPGA可编程技术，完成具有5线级流水线结构、符合IEEE 754浮点标准、可参数化为单、双精度的浮点数加法器。-Floating point adder design IP core vhd. Floating-point addition operation is used in most transport operations, combined with vhdl and EPGA programmable technology, complete with 5 line-stage pipeline structure to meet IEEE 754 floating point standards, parameters into a single, double precision floating point adder.
Platform: | Size: 154624 | Author: 凌音 | Hits:

[VHDL-FPGA-Verilog] 32-rip-adder

Description: A ripple carry adder allows you to add two 32-bit numbers
Platform: | Size: 1024 | Author: kaream | Hits:

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[WEB Code] ripple-lookahead-carryselect-adder

[Other resource] Add64

[Streaming Mpeg4] sadct

[Documents] ripple-lookahead-carryselect-adder

[ARM-PowerPC-ColdFire-MIPS] Add64

[Streaming Mpeg4] sadct

[MPI] source

[VHDL-FPGA-Verilog] 32addjiafaqi

[MPI] add_16_bcd

[VHDL-FPGA-Verilog] add_32_bcd

[VHDL-FPGA-Verilog] add(FLP)

[VHDL-FPGA-Verilog] brentkung_32

[VHDL-FPGA-Verilog] koggestone_32

[VHDL-FPGA-Verilog] CSLA_32

[VHDL-FPGA-Verilog] floating-point-adder1

[MiddleWare] ADDER

[Windows Develop] adder

[Other] adder

[VHDL-FPGA-Verilog] Floating-Point-Adder

[VHDL-FPGA-Verilog] 32-rip-adder

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