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[Other resource] 9320_18_wei

Description: File name: main.c ** Last modified Date: 2006-09-26 ** Last Version: 1.0 ** Descriptions: The main() function example template ** **------------------------------------------------------------------------------------------------------ ** Created by: ** Created date: 2006-09-16 ** Version: 1.0 ** Descriptions: The original version ** **------------------------------------------------------------------------------------------------------ ** Modified by: Driver IC:ili9320 18BIT ** Modified date: vcs320240-2006-0 ** Version: ** Descriptions:
Platform: | Size: 5508 | Author: 钟林 | Hits:

[SCM] 9320_18_wei

Description: File name: main.c ** Last modified Date: 2006-09-26 ** Last Version: 1.0 ** Descriptions: The main() function example template ** **------------------------------------------------------------------------------------------------------ ** Created by: ** Created date: 2006-09-16 ** Version: 1.0 ** Descriptions: The original version ** **------------------------------------------------------------------------------------------------------ ** Modified by: Driver IC:ili9320 18BIT ** Modified date: vcs320240-2006-0 ** Version: ** Descriptions:-File name: main.c** Last modified Date: 2006-09-26** Last Version: 1.0** Descriptions: The main () function example template****------------------------------------------------------------------------------------------------------** Created by:** Created date: 2006-09-16** Version: 1.0** Descriptions: The original version****------------------------------------------------------------------------------------------------------** Modified by: Driver IC: ili9320 18BIT** Modified date: vcs320240-2006-0** Version:** Descriptions :
Platform: | Size: 5120 | Author: 钟林 | Hits:

[VHDL-FPGA-Verilog] multiply2

Description: 18bit的booth乘法器 采用booth2编码 Wallace压缩树 以及超前进位结合进位选择的36bit高性能加法器-18bit multipliers used booth2 the booth encoding and Wallace tree compression-ahead into the location choice of high-performance 36bit adder
Platform: | Size: 5120 | Author: alex | Hits:

[VHDL-FPGA-Verilog] cf_fft_latest.tar

Description: 整个设计使用了流水线设计，运用了同步的使能和复位信号。这是一个4k点的fft。实部和虚部均为18bit，总共为36bit精度。-All designs are pipelined with a synchronous enable and reset. 18 bit precision, real and imaginary. Total is 36 bits.
Platform: | Size: 3125248 | Author: 赵恒 | Hits:

[Other Embeded program] SPI-3line-9bit-18bit

Description: SPI-3line-9bit 送18bit数据的方法+一些其他常用IC的初始化代码-SPI-3line-9bit 18bit data sent to some other commonly used methods+ IC initialization code
Platform: | Size: 1024 | Author: 陈一诗 | Hits:

[SCM] QVGA-18BIT

Description: 基于80C54测试LCM，18BIT/9BIT程序-80C54-based test LCM, 18BIT/9BIT program
Platform: | Size: 163840 | Author: 彭武 | Hits:

[Picture Viewer] NT35510-16-or-18bit

Description: 51单片机，驱动nt35510TFT屏，包含16bit，及18bit驱动方式，显示红绿蓝黑白灰阶，小图片-51 MCU, drive nt35510TFT screen in
Platform: | Size: 870400 | Author: fengming | Hits:

[SCM] HX8357B-

Description: 51单片机，驱动HX8357B TFT显示屏，支持16,18bit显示模式，显示红绿蓝黑白灰阶图片。-51 single-chip driver HX8357B TFT display, support 16,18 bit display mode, display the red, green and blue black and white gray scale images.
Platform: | Size: 382976 | Author: fengming | Hits:

[VHDL-FPGA-Verilog] Booth2-multiplier

Description: 一个18bit乘以18bit的Booth2编码的乘法器，已验证通过-A 18bit*18bit booth2 mutiplixer
Platform: | Size: 15360 | Author: yefeng | Hits:

[VHDL-FPGA-Verilog] AD4003_CTR

Description: 一个AD4003的测试/控制程序，2Ms/s，18bit的AD高速AD芯片(A AD4003 test / control program, 2Ms/s, 18bit AD high speed AD chip)
Platform: | Size: 7486464 | Author: 胜寒 | Hits:

[Embeded-SCM Develop] AT89C51-MCP3421

Description: MCP3421 12bit~18bit 的 ADC 用于微小电压采集 proteus 8 仿真 C51程序 Keil4/5编程 串口打印电压值 （可虚拟串口仿真）(MCP3421 12bit~18bit ADC for small voltage acquisition Proteus 8 simulation C51 program Keil4/5 programming serial port printing voltage value (virtual serial port simulation))
Platform: | Size: 209920 | Author: wolrd | Hits:

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