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[Documents] ripple-lookahead-carryselect-adder

Description: Ripple Adder: 16-bit 全加,半加及ripple adder的设计及VHDL程序 Carry Look ahead Adder:4, 16, 32 bits 前置进位加法器的设计方案及VHDL程序 Carry Select Adder:16 Bits 进位选择加法器的设计方案及VHDL程序-Ripple Adder : 16-bit full adder, semi-Canada and the ripple adder design and VHDL procedures Carry Look ahead Adder : 4, 16, 32 bits front rounding Adder and the VHDL design procedures Carry Select Adder : 16 Bits Progressive Choice Adder design and VHDL- sequence
Platform: | Size: 15360 | Author: 李成 | Hits:

[Embeded-SCM Develop] 16Bit

Description: 16Bit Group Ripple Adder ，protel基础的实验模拟-16Bit Group Ripple Adder, protel simulation-based experiment
Platform: | Size: 12288 | Author: zll | Hits:

[VHDL-FPGA-Verilog] ADDER

Description: simple 16-bit CSA Adder
Platform: | Size: 65536 | Author: calvin | Hits:

[VHDL-FPGA-Verilog] flowvhdl

Description: 16 bit adder source code.
Platform: | Size: 128000 | Author: midhunraj | Hits:

[VHDL-FPGA-Verilog] wallace

Description: wallace tree 用于16位乘法器的verilog 的 wallace tree代码 -wallace tree verilog file. 16bit wallace tree adder.
Platform: | Size: 2048 | Author: Zachary | Hits:

[VHDL-FPGA-Verilog] adder_csa

Description: carry select adder in verilog
Platform: | Size: 1024 | Author: Eric | Hits:

[matlab] 16bit-CLA

Description: a 16 bit carry look ahead adder verilog code
Platform: | Size: 8192 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] 16bit-CLA

Description: 16 bit carry look ahead adder verilog code
Platform: | Size: 8192 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] full-add-16bit

Description: full adder 16bit..it s okie
Platform: | Size: 23552 | Author: rihtuu | Hits:

[VHDL-FPGA-Verilog] PROJECT1-20130414-20130512

Description: 16bit adder的verilog源代码和4bit的计数器源代码-source code for 16bit adder and 4bit counter
Platform: | Size: 8192 | Author: allen wang | Hits:

[Algorithm] 16bit-ALU

Description: 16位ALU。包括超前进位加减法器、大小比较、算术逻辑位移等运算-16-bit ALU. Including lookahead adder-subtractor, size comparison, arithmetic and logic operations displacement
Platform: | Size: 1024 | Author: Fan | Hits:

[VHDL-FPGA-Verilog] adder16.v

Description: 这是自己写的16bit ripple 形式的加法器的代码，用verilog写的，如果有用，fell free to download-This is to write 16bit ripple adder form of code, verilog written, if useful, fell free to download
Platform: | Size: 1024 | Author: liuyang | Hits:

[MPI] HW-02-13210140

Description: Verilog code adder for add 2 16bit in parallel-adder for 16bit used to add two bits in parallel. this code in verilog languanger
Platform: | Size: 1024 | Author: erich | Hits:

[VHDL-FPGA-Verilog] 16Bit-Group-Ripple-Adder

Description: Verilog Testbench for 16Bit Group Ripple Adder
Platform: | Size: 29696 | Author: Raz | Hits:

[VHDL-FPGA-Verilog] cla_16bit

Description: verilog 16bit carry lookahead adder-verilog 16bit carry lookahead adder
Platform: | Size: 1024 | Author: uiop7890 | Hits:

[Communication-Mobile] adder

Description: 用hspice写了一个做了16bit kogge stone四层点操作的树形加法器静态逻辑网表，所有管子的尺寸按照0.25u的尺寸设计挂上测试文件跑以后逻辑没问题，但是按照拉贝尔那本书上讲的关于逻辑努力优化的方法优化，在输入级加了两级buffer，只对最长路径支路尺寸优化(Use HSPICE to write a 16bit kogge made stone four layer tree adder static logic netlist, all pipe sizes according to the size of design 0.25u hang test file to run after the logic is no problem, but in accordance with the method of logic optimization efforts of Labelle's book about the optimization, plus two buffer in the input stage, only the longest path branch size optimization)
Platform: | Size: 10240 | Author: 大法张 | Hits:

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